AREA-MAXIMUM EDGE LENGTH TRADE-OFF FOR VLSI LAYOUT.

被引：0
|
作者：
Blum, Norbert [1 ]
机构：
[1] Univ des Saarlandes, Saarbrueken, West Ger, Univ des Saarlandes, Saarbrueken, West Ger
来源：
Information and control | 1985年 / 66卷 / 1-2期
关键词：
INTEGRATED CIRCUITS; VLSI - Computer Aided Design;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
We construct an N-node graph G which has (i) a layout with area O(N) and maximum edge length O(N**1**/**2), (ii) a layout with area O(N**5**/**4) and maximum edge length O(N**1**/**4). We prove for 1 less than equivalent to f(N) less than equivalent to O(N**1**/**8) that any layout for G with area Nf(N) has an edge of length OMEGA (N**1**/**2/f(N) multiplied by (times) log N). Hence G has no layout which is optimal with respect to both measures.
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页码：45 / 52
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