HYSTERESIS I-V EFFECTS IN SHORT-CHANNEL SILICON MOSFET'S.

Hysteresis in I//d//s-V//d//s characteristics is observed at high drain voltages in short-channel silicon MOSFETs biased into the normally off regime, the degree of which depends on the substrate and gate biases. The MOSFET switches at this hysteresis point from subthreshold to space-charge-limited current behavior. It is proposed that this hysteresis effect is due to avalanched holes which accumulate at the gate interface, causing a deformation of the potential distribution in the substrate and the triggering of the device into space-charge-limited current behavior.