Architectural support for fine-grain multithreading on stock processors

被引：0
|
作者：
Kotikalapoodi, S.V. [1 ]
Lee, B. [1 ]
Lu, S.-L. [1 ]
Hurson, A.R. [1 ]
机构：
[1] Oregon State Univ, Corvallis, United States
来源：
Microcomputer Applications | 1996年 / 15卷 / 01期
关键词：
Computer aided design - Computer architecture - Computer networks - Reduced instruction set computing - Sequential switching;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This paper discusses some issues involved in providing efficient support for fine-grain multithreading and proposes the modifications required on a conventional processor. The design is aimed at reducing the costs associated with context-switching. The hardware modifications are kept to a minimum in order to maintain the functionality of a conventional RISC processor.
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页码：14 / 19
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