ACCURATE SIMULATION OF FLIP-FLOP TIMING CHARACTERISTICS.

被引：0

作者：

Evans, David J.

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来源：

| 1978年

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摘要：

Detailed timing analysis of flip-flops in a gate level simulator is described. The simulator detects violations of set-up time, hold time, and minimum clock, set, and reset pulse widths.

引用

页码：398 / 404

共 50 条

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