共 8 条
- [1] 82-DOLLAR BUYS CHIP WITH 2-DSPS, 32-BIT RISC, AND 44-KBYTE SRAM [J]. COMPUTER DESIGN, 1995, 34 (10): : 120 - 121
- [4] NEC ANNOUNCES 32-BIT RISC CHIP FOR EMBEDDED CONTROL APPLICATIONS [J]. ELECTRONICS-US, 1993, 66 (03): : 8 - 8
- [5] A Flexible Debugger for a RISC-V Based 32-bit System-on-Chip [J]. 2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2020,
- [8] Implementation of a 32-bit RISC processor for the data-intensive architecture processing-in-memory chip [J]. IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES, AND PROCESSORS, PROCEEDINGS, 2002, : 163 - 172