Efficient performance-driven layout algorithm

被引：0
|
作者：
Chen, Yunkang [1 ]
Cao, Jian [1 ]
Xu, Hong [1 ]
Xu, Dongmin [1 ]
机构：
[1] Tsinghua Univ, Beijing, China
来源：
Qinghua Daxue Xuebao/Journal of Tsinghua University | 1995年 / 35卷 / 01期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
12
引用
收藏
页码：10 / 16
相关论文
共 50 条
  • [11] Parallel genetic algorithm for performance-driven VLSI routing
    Lienig, Jens
    IEEE Transactions on Evolutionary Computation, 1997, 1 (01): : 29 - 39
  • [12] An interconnect allocation algorithm for performance-driven datapath synthesis
    Kim, YN
    Lee, HD
    Hwang, SY
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 1996, 6 (04) : 403 - 423
  • [13] Performance-driven Routing Methodology with Incremental Placement Refinement for Analog Layout Design
    Chi, Hao-Yu
    Chang, Han-Chung
    Yang, Chih-Hsin
    Liu, Chien-Nan
    Jou, Jing-Yang
    PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, : 1218 - 1223
  • [14] Performance-Driven Maintenance
    不详
    POWER, 2013, 157 (05) : 18 - 19
  • [15] A NEW PERFORMANCE-DRIVEN GLOBAL ROUTING ALGORITHM FOR GATE ARRAY
    XUE, TX
    FUJII, T
    KUH, ES
    VLSI 93, 1994, 42 : 321 - 330
  • [16] Performance-driven MCM partitioning through an adaptive genetic algorithm
    Raman, S
    Patnaik, LM
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1996, 4 (04) : 434 - 444
  • [17] A novel performance-driven placement based on hybrid genetic algorithm
    Yoshikawa, Masaya
    Terai, Hidekazu
    2005 IEEE INTERNATIONAL CONFERENCE ON MECHATRONICS AND AUTOMATIONS, VOLS 1-4, CONFERENCE PROCEEDINGS, 2005, : 1203 - 1208
  • [18] Force-directed performance-driven placement algorithm for FPGAs
    Li, H
    Mak, WK
    Katkoori, S
    VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, 2004, : 193 - 198
  • [19] A performance-driven layer assignment algorithm for multiple interconnect trees
    Saxena, P
    Liu, CL
    1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS, 1998, : 124 - 127
  • [20] A performance-driven logic emulation system: FPGA network design and performance-driven partitioning
    Kim, CH
    Shin, HC
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (05) : 560 - 568
12345