Configurations for IDDQ-testable PLAs

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Philips Research Laboratories, Eindhoven, Netherlands ^{[1
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IEEE Des Test Comput | / 2卷 / 58-65期

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共 12 条

[1] Configurations for IDDQ-testable PLAs
Sachdev, M
Kerkhoff, H
IEEE DESIGN & TEST OF COMPUTERS, 1999, 16 (02): : 58 - 65
[2] IDDQ testable design of static CMOS PLAs
Hashizume, M
Hoshika, H
Yotsuyanagi, H
Tamesada, T
2000 IEEE INTERNATIONAL WORKSHOP ON DEFECT BASED TESTING, PROCEEDINGS, 2000, : 70 - 75
[3] ON THE DESIGN OF PSEUDOEXHAUSTIVE TESTABLE PLAS
HA, DS
REDDY, SM
IEEE TRANSACTIONS ON COMPUTERS, 1988, 37 (04) : 468 - 472
[4] A NEW APPROACH TO THE DESIGN OF TESTABLE PLAS
REDDY, SM
HA, DS
IEEE TRANSACTIONS ON COMPUTERS, 1987, 36 (02) : 201 - 211
[5] Testable static CMOS PLA for IDDQ testing
Hashizume, M.
Hoshika, H.
Yotsuyanagi, H.
Tamesada, T.
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2001, E84-A (06) : 1488 - 1495
[6] I-DDQ testable dynamic PLAs
Sachdev, M
Kerkhoff, H
IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, DIGEST OF PAPERS, 1997, : 17 - 22
[7] Testable static CMOS PLA for IDDQ testing
Hashizume, M
Hoshika, H
Yotsuyanagi, H
Tamesada, T
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2001, E84A (06): : 1488 - 1495
[8] SCHEME FOR DESIGNING CONCURRENT CHECKING AND EASILY TESTABLE PLAS
TAO, DL
LALA, PK
HARTMANN, CRP
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1990, 137 (06): : 442 - 450
[9] A high performance IDDQ testable cache for scaled CMOS technologies
Bhunia, S
Li, H
Roy, K
PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS 02), 2002, : 157 - 162
[10] Random pattern testable design with partial circuit duplication and IDDQ testing
Yokoyama, Hiroshi
Wen, Xiaoqing
Tamamoto, Hideo
Systems and Computers in Japan, 1999, 30 (05): : 18 - 27

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