共 50 条
- [1] Chip-Package Co-Simulation with Multiscale Structures 2008 IEEE-EPEP ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2008, : 317 - 320
- [3] Chip-package co-design of a 4.7 GHz VCO ICM'99: ELEVENTH INTERNATIONAL CONFERENCE ON MICROELECTRONICS - PROCEEDINGS, 1999, : 145 - 148
- [4] Chip-package co-implementation of a triple DES processor IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2004, 27 (01): : 194 - 202
- [5] System Aware Floorplanning for Chip-Package Co-design 2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS, 2023,
- [6] Chip-package co-design of a 4.7 GHz VCO 2000 HD INTERNATIONAL CONFERENCE ON HIGH-DENSITY INTERCONNECT AND SYSTEMS PACKAGING, 2000, 4217 : 301 - 306
- [7] Analysis of VCO jitter in chip-package co-design 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS, 2002, : 181 - 184
- [8] Chip-Package Co-design for Optimization of 5.8GHz CMOS LNA Performance 2017 18TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2017, : 1027 - 1030
- [10] Chip-Package Thermal Co-Simulation Technique for Thermally Aware Chip Design 2010 12TH IEEE INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONIC SYSTEMS, 2010,