Distributed fault simulation with collaborative load balancing for vlsi circuits

被引：0
|
作者：
Ivask, Eero [1 ]
Devadze, Sergei [1 ]
Ubar, Raimund [1 ]
机构：
[1] Tallinn University of Technology, Estonia
来源：
Scalable Computing | 2011年 / 12卷 / 01期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：153 / 163
相关论文
共 50 条
  • [1] DISTRIBUTED FAULT SIMULATION WITH COLLABORATIVE LOAD BALANCING FOR VLSI CIRCUITS
    Ivask, Eero
    Devadze, Sergei
    Ubar, Raimund
    [J]. SCALABLE COMPUTING-PRACTICE AND EXPERIENCE, 2011, 12 (01): : 153 - 163
  • [2] Collaborative Distributed Fault Simulation for Digital Electronic Circuits
    Ivask, Eero
    Devadze, Sergei
    Ubar, Raimund
    [J]. INTELLIGENT DISTRIBUTED COMPUTING IV, 2010, 315 : 67 - 76
  • [3] FAULT SIMULATION IN CMOS VLSI CIRCUITS
    ZAGHLOUL, ME
    GOBOVIC, D
    [J]. IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1991, 138 (04): : 203 - 212
  • [4] Adaptive, distributed load management in balancing circuits
    Kamper, Andreas
    Schmeck, Hartmut
    [J]. Informatik-Spektrum, 2012, 35 (02) : 102 - 111
  • [5] Computational load balancing for distributed simulation
    White, E
    [J]. MILITARY, GOVERNMENT, AND AEROSPACE SIMULATION, 1997, 29 (04): : 203 - 207
  • [6] LBFT: Load Balancing and Fault Tolerance in distributed controllers
    Mahjoubi, Ayeh
    Zeynalpour, Omid
    Eslami, Benyamin
    Yazdani, Nasser
    [J]. 2019 INTERNATIONAL SYMPOSIUM ON NETWORKS, COMPUTERS AND COMMUNICATIONS (ISNCC 2019), 2019,
  • [7] An adaptive load balancing middleware for distributed simulation
    Bononi, Luciano
    Bracuto, Michele
    D'Angelo, Gabriele
    Donatiello, Lorenzo
    [J]. FRONTIERS OF HIGH PERFORMANCE COMPUTING AND NETWORKING - ISPA 2006 WORKSHOPS, PROCEEDINGS, 2006, 4331 : 873 - +
  • [8] Simulation methods for load balancing in distributed computing
    Ivanisenko, Igor
    Volk, Maksym
    [J]. 2017 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS), 2017,
  • [9] System level test generation and fault simulation for VLSI circuits
    Ma, YH
    Sun, YH
    Chen, HY
    [J]. 1996 2ND INTERNATIONAL CONFERENCE ON ASIC, PROCEEDINGS, 1996, : 396 - 399
  • [10] Efficient partitioning method for distributed logic simulation of VLSI circuits
    Guettaf, A
    Bazargan-Sabet, P
    [J]. 31ST ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS, 1998, : 196 - 201
12345