Design & performance analysis of low power reversible residue adder

Adder circuits play an important role in reversible computation, which is helpful in diverse areas such as Low power CMOS design, quantum computing and nano technology. A reversible gate has equal number of inputs and outputs; so that, there should be one to one mapping between input and output vectors. Therefore, the input vector states can be always uniquely recovered from the output vector states. This paper presents a reversible residue circuit that requires only two reversible gates i.e. Modified TSG gate and Modified Fredkin Gate and consumes Low power. The design provides a significant reduction in the quantum cost of the circuit compared to the existing Residue Adder reversible logic implementation. For coding of design, VHDL language has been used. Xilinx design tool 14.4 and Xilinx project navigator tools are used for synthesis and simulation purpose. © 2016 SERSC.