Embedded test complements boundary scan

被引：0

作者：

Nelson, Rick

机构：

来源：

EE: Evaluation Engineering | 2012年 / 51卷 / 10期

关键词：

Timing circuits;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

引用

页码：22 / 26

共 50 条

[1] Embedded boundary scan test bus controller
Jiang, ZG
Lei, J
Yan, XL
ICEMI'2003: PROCEEDINGS OF THE SIXTH INTERNATIONAL CONFERENCE ON ELECTRONIC MEASUREMENT & INSTRUMENTS, VOLS 1-3, 2003, : 1002 - 1005
[2] Embedded boundary scan
Bennetts, RG
IEEE DESIGN & TEST OF COMPUTERS, 2003, 20 (02): : 20 - 20
[3] Boundary-scan test realization based on embedded system
Cui Wei
Feng Chang-Jiang
Mao Zhijun
ISTM/2009: 8TH INTERNATIONAL SYMPOSIUM ON TEST AND MEASUREMENT, VOLS 1-6, 2009, : 283 - 286
[4] Embedded test technique extends 1149.1 boundary-scan architecture
Desposito, J
ELECTRONIC DESIGN, 1999, 47 (24) : 50 - 50
[5] Socillator test: A delay test scheme for embedded ICs in the boundary-scan environment
Tan, TJ
Lee, CL
19TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2001, : 158 - 162
[6] A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores
Chiu, Geng-Ming
Li, James Chien-Mo
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (01) : 126 - 134
[7] Boundary scan: The Internet of test
Wondolowski, M
Bennetts, B
Ley, A
IEEE DESIGN & TEST OF COMPUTERS, 1999, 16 (03): : 34 - 43
[8] Boundary scan test standards
Ashenden, PJ
IEEE DESIGN & TEST OF COMPUTERS, 2003, 20 (01): : 91 - 92
[9] Boundary scan test in practice
Australian Electronics Engineering, 1992, 24 (04):
[10] THE IMPACT OF BOUNDARY SCAN ON BOARD TEST
PARKER, KP
IEEE DESIGN & TEST OF COMPUTERS, 1989, 6 (04): : 18 - 30