共 50 条
- [43] A priority buffering queue architecture in high-speed switch DCABES 2001 PROCEEDINGS, 2001, : 188 - 191
- [44] Control architecture for high capacity multistage photonic switch circuits JOURNAL OF OPTICAL NETWORKING, 2007, 6 (02): : 180 - 188
- [45] Architecture and performance of a next-generation Optical Burst Switch (OBS) 2006 3RD INTERNATIONAL CONFERENCE ON BROADBAND COMMUNICATIONS, NETWORKS AND SYSTEMS, VOLS 1-3, 2006, : 1112 - +
- [46] A performance enhanced dual-switch network-on-chip architecture IPSJ Trans. Syst. LSI Des. Methodol., (85-94):
- [49] Architecture and performance analysis of the multicast Balanced Gamma switch for broadband communications 2006 IEEE INTERNATIONAL CONFERENCE ON COMPUTER SYSTEMS AND APPLICATIONS, VOLS 1-3, 2006, : 381 - +
- [50] High Throughput Architecture for High Performance NoC ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 2241 - 2244