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- [43] Analysis of Failure Mechanisms in Erased State of Sub 20-nm NAND Flash Memory PROCEEDINGS OF THE 2014 44TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2014), 2014, : 58 - 61
- [44] An ultra-thin hybrid floating gate concept for Sub-20nm NAND flash technologies 2011 3rd IEEE International Memory Workshop, IMW 2011, 2011,
- [46] Interface and oxide trap analysis at tunnel oxide of NAND flash memory with excluding the effect of floating gate 2016 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW), 2016, : 90 - 91
- [47] Challenges and Limitations of NAND Flash Memory Devices Based on Floating Gates 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 420 - 423
- [48] A BE-SONOS (bandgap engineered SONOS) NAND for post-floating gate era flash memory 2007 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PAPERS, 2007, : 16 - +