Low cost quantum realization of reversible multiplier circuit

被引：67
|
作者：
Islam, M.S. [1 ]
Rahman, M.M. [1 ]
Begum, Z. [1 ]
Hafiz, M.Z. [1 ]
机构：
[1] Institute of Information Technology, University of Dhaka, Dhaka-1000, Bangladesh
来源：
Information Technology Journal | 2009年 / 8卷 / 02期
关键词：
D O I：
10.3923/itj.2009.208.213
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：208 / 213
相关论文
共 50 条
  • [1] Low Quantum Cost Realization of Reversible Binary-Coded-Decimal Adder
    Thabah, Sheba Diamond
    Saha, Prabir
    INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE AND DATA SCIENCE, 2020, 167 : 1437 - 1443
  • [2] Quantum Cost Optimization for Reversible Sequential Circuit
    Al Mamun, Selim
    Menville, David
    INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS, 2013, 4 (12) : 15 - 21
  • [3] OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT
    Haghparast, Majid
    Mohammadi, Majid
    Navi, Keivan
    Eshghi, Mohammad
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2009, 18 (02) : 311 - 323
  • [4] A Novel Approach for Reversible Realization of 4 x 4 Bit Vedic Multiplier Circuit
    Shukla, Vandana
    Singh, O. P.
    Mishra, G. R.
    Tiwari, R. K.
    ADVANCES IN VLSI, COMMUNICATION, AND SIGNAL PROCESSING, 2020, 587 : 733 - 745
  • [5] An Optimized Low-Cost 4 x 4 Multiplier Circuit Design Using Reversible Logic Gates
    Bhattacharya, Sriparna
    Bhattacharya, Soham
    Adak, Asima
    Sen, Anindya
    ADVANCED NETWORK TECHNOLOGIES AND INTELLIGENT COMPUTING, ANTIC 2022, PT I, 2023, 1797 : 263 - 281
  • [6] A Novel Approach for Reversible Realization of 8-Bit Adder-Subtractor Circuit with Optimized Quantum Cost
    Shukla, Vandana
    Singh, O. P.
    Mishra, G. R.
    Tiwari, R. K.
    FIRST INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN ENGINEERING, TECHNOLOGY AND SCIENCE - ICETETS 2016, 2016,
  • [7] A Novel Design of Reversible Multiplier Circuit
    Moallem, P.
    Ehsanpour, M.
    INTERNATIONAL JOURNAL OF ENGINEERING, 2013, 26 (06): : 577 - 585
  • [8] Optimization of Quantum Cost for Low Energy Reversible Signed/Unsigned Multiplier Using Urdhva-Tiryakbhyam Sutra
    Elmenyawi M.A.
    Tawfeek R.M.
    Computer Systems Science and Engineering, 2023, 46 (02): : 1827 - 1844
  • [9] Transistor realization of reversible "ZS" series gates and reversible array multiplier
    Zhou, Rigui
    Shi, Yang
    Wang, Hui'an
    Cao, Jian
    MICROELECTRONICS JOURNAL, 2011, 42 (02) : 305 - 315
  • [10] Improving the quantum cost of NCT-based reversible circuit
    Rasha Montaser
    Ahmed Younes
    Mahmoud Abdel-Aty
    Quantum Information Processing, 2015, 14 : 1249 - 1263
12345