Bit-Serial SRAM Computing In-Memory Based on Primary and Complemental Code Implementation

Possessing a problem of unable non-convolution computation independently in most computing inmemorys (CIMs), a general-purpose hybrid CIM was proposed based on combining the transposed 8T cells with vector-based bit-serial in-memory operations. The proposed system was designed to facilitate multiply-and-accumulate (MAC) operations for integers/decimals and positive/negative numbers of varying bit widths by utilizing the primary multiplication, complement addition and overflow activation. It also was arranged to support pooling and activation operations separately, offering the essential flexibility and programmability for the development of various software algorithms ranging from neural networks to signal processing, and minimizing data transmission over the bus. Results show that the proposed CIM method can provide a throughput of 71.3 GOPs and an energy efficiency of 20.63 TOPS/W for 8-bit operations under the condition of at 1.2 V and 500 MHz, supporting convolutional operations with flexible bit-widths, reducing data shifts and improving energy efficiency and overall performance. © 2024 Beijing Institute of Technology. All rights reserved.