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- [1] Wafer-level integration of self-aligned high aspect ratio silicon 3D structures using the MACE method with Au, Pd, Pt, Cu, and Ir BEILSTEIN JOURNAL OF NANOTECHNOLOGY, 2020, 11 : 1439 - 1449
- [3] Wafer-Level Wet Etching of High-Aspect-Ratio Through Silicon Vias (TSVs) with High Uniformity and Low Cost for Silicon Interposers with High-Density Interconnect of 3D Packaging 2015 IEEE 65TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2015, : 1417 - 1422
- [4] Implementation of SOG devices with embedded through-wafer silicon vias using a glass reflow process for wafer-level 3D MEMS integration MEMS 2008: 21ST IEEE INTERNATIONAL CONFERENCE ON MICRO ELECTRO MECHANICAL SYSTEMS, TECHNICAL DIGEST, 2008, : 802 - +
- [8] Bumpless Build Cube (BBCube): High-Parallelism, High-Heat-Dissipation and Low-Power Stacked Memory Using Wafer-Level 3D Integration Process 2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY, 2020,
- [9] Full 300 mm Electrical Characterization of 3D Integration Using High Aspect Ratio (10:1) Mid-Process Through Silicon Vias 2015 IEEE 17TH ELECTRONICS PACKAGING AND TECHNOLOGY CONFERENCE (EPTC), 2015,