Development of a new design simulator for poly-Si TFTs to optimize the lightly doped drain structure

被引:0
|
作者
Nanno, Yutaka [1 ]
Senda, Kohji [1 ]
Tsutsu, Hiroshi [1 ]
Uchiike, Heiju [1 ]
机构
[1] Matsushita Elec. Industrial Co., Ltd, Display Devices Development Center, 3-1-1 Yagumo-Nakamachi, Moriguichi, Osaka 570-8501, Japan
关键词
Density of state - Lightly doped drain structure - Photo induced current - Photomask aligned process;
D O I
10.1889/1.1827831
中图分类号
学科分类号
摘要
引用
收藏
页码:101 / 106
相关论文
共 50 条
  • [21] Gate-overlapped lightly doped drain poly-Si thin-film transistors for large area AMLCD
    Choi, KY
    Lee, JW
    Han, MK
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (06) : 1272 - 1279
  • [22] Characterization of trap density at grain boundaries using doped poly-Si TFTs
    Yoshino, Takuto
    Kimura, Mutsumi
    Sameshima, Toshiyuki
    IDW '06: PROCEEDINGS OF THE 13TH INTERNATIONAL DISPLAY WORKSHOPS, VOLS 1-3, 2006, : 1671 - +
  • [23] Modeling of the parasitic resistance effect in poly-Si TFTs with LDD structure
    Kao, Shih-Chin
    Zan, Hsiao Wen
    Chen, Shih-Ching
    IDMC 05: PROCEEDINGS OF THE INTERNATIONAL DISPLAY MANUFACTURING CONFERENCE 2005, 2005, : 529 - 532
  • [24] The effect of lightly doped drain in short channel low temperature poly-Si thin film transistor for active matrix display
    Park, J. H.
    Nam, W. J.
    Lee, J. H.
    Lee, K. Y.
    Yoo, K. J.
    Park, H. H.
    Han, M. K.
    IDW/AD '05: PROCEEDINGS OF THE 12TH INTERNATIONAL DISPLAY WORKSHOPS IN CONJUNCTION WITH ASIA DISPLAY 2005, VOLS 1 AND 2, 2005, : 1233 - 1234
  • [25] Control of Drain Induced Barrier Lowering in short channel poly-Si TFTs for AMOLED displays
    Byun, Ki Yeol
    Jang, Seunghyun
    Son, Byung-Taek
    Yang, Yong-Ho
    Lee, Yongsoo
    Kim, Yeon-Tae
    Cho, Hyunwoo
    Yoo, Moon-Hyun
    PROCEEDINGS OF 2013 TWENTIETH INTERNATIONAL WORKSHOP ON ACTIVE-MATRIX FLATPANEL DISPLAYS AND DEVICES (AM-FPD 13): TFT TECHNOLOGIES AND FPD MATERIALS, 2013, : 203 - 206
  • [26] OI-ELA poly-Si TFTs for eliminating residual source/drain junction defects
    Nam, WJ
    Park, KC
    Jung, SH
    Hanz, MK
    ELECTROCHEMICAL AND SOLID STATE LETTERS, 2005, 8 (02) : G41 - G43
  • [27] A Unified Drain Current Model for Poly-Si and a-InGaZnO TFTs under Different Temperatures
    Han, Zhiyuan
    Wang, Mingxing
    Wu, Yong
    Zhou, Haiqin
    He, Jin
    PROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015), 2015, : 80 - 83
  • [28] Analysis of hot carrier effects in low temperature poly-Si TFTs using device simulator
    Uraoka, Y
    Katayama, T
    Fuyuki, T
    Kawamura, T
    Tsuchihashi, Y
    ICMTS 2001: PROCEEDINGS OF THE 2001 INTERNATIONAL CONFERENCE ON MICROELECTRONIC TEST STRUCTURES, 2001, : 251 - 256
  • [29] A comparative study of n-channel low temperature poly-Si thin-film transistors with a body terminal or a lightly-doped-drain structure
    Wu, Yanwen
    Wang, Mingxiang
    Wang, Huaisheng
    Zhang, Dongli
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2018, 33 (02)
  • [30] Novel offset-gated bottom gate poly-Si TFTs with a combination structure of ultrathin channel and raised source/drain
    Kang, Il-Suk
    Han, Shin-Hee
    Joo, Seung-Ki
    IEEE ELECTRON DEVICE LETTERS, 2008, 29 (03) : 232 - 234