共 50 条
- [1] Design tradeoffs using truncated multipliers in FIR filter implementations ADVANCED SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, AND IMPLEMENTATIONS XII, 2002, 4791 : 357 - 368
- [3] Time-multiplexed FIR filter design using group CSD(GCSD) multipliers Transactions of the Korean Institute of Electrical Engineers, 2010, 59 (02): : 452 - 456
- [5] Area and delay efficient RNS-based FIR filter design using fast multipliers Measurement: Sensors, 2024, 31
- [6] FILTER-LENGTH WORD-LENGTH TRADEOFFS IN FIR DIGITAL FILTER DESIGN. IEEE Transactions on Acoustics, Speech, and Signal Processing, 1980, ASSP-28 (06): : 739 - 744
- [7] FILTER-LENGTH WORD-LENGTH TRADEOFFS IN FIR DIGITAL-FILTER DESIGN IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1980, 28 (06): : 739 - 744
- [8] Efficient parallel FIR filter implementations using frequency spectrum characteristics ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6, 1998, : D354 - D358
- [9] ON FIR DIGITAL-FILTER IMPLEMENTATIONS FOR INTERPOLATION IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1981, 29 (02): : 315 - 317
- [10] Design tradeoffs in CMOS FIR filters 1996 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, CONFERENCE PROCEEDINGS, VOLS 1-6, 1996, : 3260 - 3263