A new hardware implementation of Manchester line decoder

被引：0

作者：

Khorwat, Ibrahim A. ^{[1
,2
]}

Naas, Nabil ^{[1
]}

机构：

[1] Electrical and Electronic Engineering Department, Alfatah University, Libya

[2] Aljeel Aljadeed For Technology Company, Libya

来源：

World Academy of Science, Engineering and Technology | 2010年 / 45卷

关键词：

Timing circuits;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

In this paper, we present a simple circuit for Manchester decoding and without using any complicated or programmable devices. This circuit can decode 90kbps of transmitted encoded data; however, greater than this transmission rate can be decoded if high speed devices were used. We also present a new method for extracting the embedded clock from Manchester data in order to use it for serial-to-parallel conversion. All of our experimental measurements have been done using simulation.

引用

页码：262 / 266

共 50 条

[1] A new hardware implementation of Manchester line decoder
Khorwat, Ibrahim A.
Naas, Nabil
World Academy of Science, Engineering and Technology, 2010, 69 : 262 - 266
[2] Implementation of Manchester decoder utilizing DPLL
School of Instrument Science and Opto-electronics Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100083, China
Yi Qi Yi Biao Xue Bao, 2007, SUPP. 4 (142-145):
[3] A New LDPC Decoder Hardware Implementation with Improved Error Rates
Schlaefer, P.
Scholl, S.
Leonardi, E.
Wehn, N.
2015 IEEE JORDAN CONFERENCE ON APPLIED ELECTRICAL ENGINEERING AND COMPUTING TECHNOLOGIES (AEECT), 2015,
[4] Implementation of Turbo/MAP decoder hardware
Wang, Xue-Dong
Yang, Hua
Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology, 2002, 34 (02): : 173 - 176
[5] Efficient Hardware Implementation of the LEDAcrypt Decoder
Koleci, Kristjane
Santini, Paolo
Baldi, Marco
Chiaraluce, Franco
Martina, Maurizio
Masera, Guido
IEEE ACCESS, 2021, 9 : 66223 - 66240
[6] Hardware implementation of the LDPC decoder in the FPGA structure
Kuc, Mateusz
Sulek, Wojciech
Kania, Dariusz
PRZEGLAD ELEKTROTECHNICZNY, 2019, 95 (03): : 58 - 62
[7] Digital Image Decoder for Efficient Hardware Implementation
Savic, Goran
Prokin, Milan
Rajovic, Vladimir
Prokin, Dragana
SENSORS, 2022, 22 (23)
[8] Hardware Implementation of Multiple Vector Quantization Decoder
Shigei, Noritaka
Miyajima, Hiromi
Hashiguchi, Shingo
Maeda, Michiharu
Ma, Lixin
INTERNATIONAL JOURNAL OF COMPUTER SCIENCE AND NETWORK SECURITY, 2008, 8 (11): : 54 - 61
[9] A new design and implementation of hardware accelerator for line detection
Chen, Ching-Han
Luoh, Leh
Guo, Min-Hao
MICROPROCESSORS AND MICROSYSTEMS, 2018, 61 : 179 - 197
[10] Hardware-software implementation of HEVC decoder on Zynq
Lella Aicha Ayadi
Hassen Loukil
Mohamed Ali Ben Ayed
Nouri Masmoudi
Multimedia Tools and Applications, 2020, 79 : 7685 - 7703

← 1 2 3 4 5 →