共 50 条
- [32] A reconfigurable architecture for a class of digital signal/image processing applications 2001 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS I AND II, CONFERENCE PROCEEDINGS, 2001, : 71 - 74
- [33] Metrics for digital signal processing architectures characterization: Remanence and scalability COMPUTER SYSTEMS: ARCHITECTURES, MODELING, AND SIMULATION, 2004, 3133 : 128 - 137
- [34] Very long instruction word architectures for digital signal processing 1997 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS I - V: VOL I: PLENARY, EXPERT SUMMARIES, SPECIAL, AUDIO, UNDERWATER ACOUSTICS, VLSI; VOL II: SPEECH PROCESSING; VOL III: SPEECH PROCESSING, DIGITAL SIGNAL PROCESSING; VOL IV: MULTIDIMENSIONAL SIGNAL PROCESSING, NEURAL NETWORKS - VOL V: STATISTICAL SIGNAL AND ARRAY PROCESSING, APPLICATIONS, 1997, : 583 - 586
- [35] Radar Signal Deinterleaving in Electronic Warfare Systems: A Combined Approach IEEE ACCESS, 2023, 11 : 142043 - 142061
- [36] Deep Learning for Radar Signal Detection in Electronic Warfare Systems 2020 IEEE RADAR CONFERENCE (RADARCONF20), 2020,
- [38] Porting of parallel applications to reconfigurable computer systems with various architectures and configurations 2016 5TH INTERNATIONAL CONFERENCE ON INFORMATICS, ELECTRONICS AND VISION (ICIEV), 2016, : 1122 - 1127
- [39] Signal processing for multiuser wireless systems on reconfigurable platforms RECONFIGURABLE TECHNOLOGY: FPGAS AND RECONFIGURABLE PROCESSORS FOR COMPUTING AND COMMUNICATIONS III, 2001, 4525 : 161 - 172
- [40] Features of the construction of effective computer systems for digital signal processing based on systolic processors Telecommunications and Radio Engineering (English translation of Elektrosvyaz and Radiotekhnika), 1992, 47 (07): : 85 - 91