The allocation of DMA buffer and its comparison

被引:0
|
作者
机构
来源
| 2001年 / Huazhong University of Science and Technology卷 / 29期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [41] THE ALLOCATION OF INTERSTAGE BUFFER CAPACITIES IN PRODUCTION LINES
    ALTIOK, T
    STIDHAM, S
    IIE TRANSACTIONS, 1983, 15 (04) : 292 - 299
  • [42] Approximating the Buffer Allocation Problem using epochs
    Pedersen, Jan Baekgaard
    Brodsky, Alex
    PROCEEDINGS OF THE 18TH IASTED INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED COMPUTING AND SYSTEMS, 2006, : 50 - +
  • [43] Server allocation for zero buffer tandem queues
    Yarmand, Mohammad H.
    Down, Douglas G.
    EUROPEAN JOURNAL OF OPERATIONAL RESEARCH, 2013, 230 (03) : 596 - 603
  • [44] Network Redundancy Elimination by Dynamic Buffer Allocation
    Yang, Chao
    Shi, Hua
    Xue, Guangtao
    Zhu, Hongzi
    Qian, Chen
    2014 IEEE 17TH INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE AND ENGINEERING (CSE), 2014, : 1109 - 1114
  • [45] A resource and timing optimized PCIe DMA architecture using FPGA internal data buffer
    Zhao, Yingxiao
    Liu, Xin
    Yang, Jiong
    IEICE ELECTRONICS EXPRESS, 2019, 16 (01):
  • [46] Unpaced Merging Lines With Uneven Buffer Allocation
    Shaaban, Sabry
    McNamara, Tom
    Dmitriev, Viatcheslav
    IFAC PAPERSONLINE, 2017, 50 (01): : 1093 - 1100
  • [47] Buffer allocation model based on a single simulation
    Roser, C
    Nakano, M
    Tanaka, M
    PROCEEDINGS OF THE 2003 WINTER SIMULATION CONFERENCE, VOLS 1 AND 2, 2003, : 1238 - 1246
  • [48] BUFFER SPACE ALLOCATION IN AUTOMATED ASSEMBLY LINES
    SMITH, JM
    DASKALAKI, S
    OPERATIONS RESEARCH, 1988, 36 (02) : 343 - 358
  • [49] Rate allocation and buffer management for differentiated services
    Liebeherr, J
    Christin, N
    COMPUTER NETWORKS, 2002, 40 (01) : 89 - 110
  • [50] Buffer and Register Allocation for Memory Space Optimization
    Youcef Bouchebaba
    Bruno Girodias
    Fabien Coelho
    Gabriela Nicolescu
    El mostapha Aboulhamid
    The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 2007, 49 : 123 - 138