Low-cost FPGA-based multi-channel TDC with high resolution and density for time-of-flight detectors

被引：0
|
作者：
Wang, Xinpeng [1 ,2 ]
Yang, Haibo [1 ,3 ]
Xia, Xiaolin [1 ,3 ]
Zou, Chaojie [1 ,3 ]
Su, Yangzhou [1 ,3 ]
Sun, Wenchao [1 ,3 ]
Wang, Shikai [1 ,2 ]
Zhao, Yun [2 ]
Zhao, Chengxin [1 ,3 ]
机构：
[1] Institute of Modern Physics, Chinese Academy of Sciences, Lanzhou,730000, China
[2] College of Physics and Electronic Engineering, Northwest Normal University, Lanzhou,730070, China
[3] School of Nuclear Science and Technology, University of Chinese Academy of Sciences, Beijing,100049, China
来源：
Journal of Instrumentation | 2024年 / 19卷 / 11期
基金：
中国国家自然科学基金;
关键词：
Detector readout - Digital converters - Digital electronic circuits - Digital signal processing - Digital signals - Field programmables - Front end - Front-end electronic for detector readout - Programmable gate array - Signal-processing;
D O I：
10.1088/1748-0221/19/11/C11008
中图分类号：
学科分类号：
摘要：
The Time-to-Digital Converter (TDC) is widely used for precise time interval measurements and play a critical role in Time-of-Flight (ToF) applications. In this paper, we present the design of a 64-channel leading-edge and trailing-edge TDC based on a Field-Programmable Gate Array (FPGA). This TDC is implemented on a Xilinx Kintex-7 XC7K410T-2FFG900I FPGA and consists of modules including a coarse counter, pulse generator, tapped delay line, decomposition encoder, and calibrator. To better evaluate its performance, we designed a multi-channel hardware verification board. According to laboratory test results, the timing precision has a root mean square (RMS) value of 6.69 ps, and a least significant bit (LSB) of 2.99 ps. The experimental results confirm that our TDC design achieves excellent timing precision. © 2024 IOP Publishing Ltd and Sissa Medialab. All rights, including for text and data mining, AI training, and similar technologies, are reserved.
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