DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS

被引：0
|
作者：
Ieong, MeiKei [1 ]
Wong, H.-S.Philip [1 ]
Taur, Yuan [1 ]
Oldiges, Phil [1 ]
Frank, David [1 ]
机构：
[1] IBM SRDC, Hopewell Junction, United States
来源：
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD | 2000年
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摘要：
15
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页码：147 / 150
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