Assessment of via reliability for interconnect layouts

被引：0
|
作者：
SiTD, Texas Instruments Inc., MS366, 13121 TI BL VD, Dallas, TX 75243, United States [1 ]
机构：
来源：
Adv. Metallization Conf. (AMC) | / 667-671期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Metals
引用
收藏
相关论文
共 50 条
  • [41] Reliability Testing of Advanced Interconnect Materials
    Keller, R. R.
    Strus, M. C.
    Chiaramonti, A. N.
    Kim, Y. L.
    Jung, Y. J.
    Read, D. T.
    FRONTIERS OF CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2011, 2011, 1395
  • [42] The reliability nomograph - Graphical predictor of package/module interconnect reliability
    Iannuzzelli, R
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART A, 1997, 20 (02): : 146 - 151
  • [43] Reliability Investigations of Down-stream Copper Interconnect with Different Tungsten-VIA Structures
    Teng, An-Shun
    Tu, Ronnie
    Chen, Robyn
    Lee, Ming-Yi
    Kuo, Albert
    Dai, Allen
    Lee, Shih-Chin
    Wen, Thomas
    Han, Bernie
    Lu, Chih-Yuan
    2012 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP FINAL REPORT, 2012, : 36 - 40
  • [44] Reliability Assessment and Physical Failure Analysis of Nanoscale Hard-Mask-Etching Al Interconnect
    Lee, Ming-Yi
    Teng, An-Shun
    Tu, Chia-Hao
    Kuo, Li-Kuang
    Dai, Sheng-Qian
    Shine, Chia-Chien
    Yen, Te-Chi
    Lee, Hong-Ji
    Lu, Chih-Yuan
    2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012,
  • [45] Graph layouts via layered separators
    Dujmovic, Vida
    JOURNAL OF COMBINATORIAL THEORY SERIES B, 2015, 110 : 79 - 89
  • [46] Reliability Performance of Different Layouts of Wide Metal Tracks
    Kludt, Joerg
    Weide-Zaage, Kirsten
    Ackermann, Markus
    Kovacs, Christian
    Hein, Verena
    2014 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2014,
  • [47] Optimization of flip chip interconnect reliability using a variable compliance interconnect design
    Tay, Andrew A. O.
    Sun, Wei
    EPTC 2006: 8TH ELECTRONIC PACKAGING TECHNOLOGY CONFERENCE, VOLS 1 AND 2, 2006, : 133 - 137
  • [48] Interconnect-Centric High Level Synthesis for Enhanced Layouts with Reduced Wire Length
    Parakh, Priyank
    Mullassery, Divya
    Chandrashekar, Anand
    Koc, Hakduran
    Dal, Deniz
    Mansouri, Nazanin
    IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II, 2006, : 595 - +
  • [49] Unreinforced masonry walls with irregular opening layouts: reliability of equivalent-frame modelling for seismic vulnerability assessment
    Manuel Berti
    Luca Salvatori
    Maurizio Orlando
    Paolo Spinelli
    Bulletin of Earthquake Engineering, 2017, 15 : 1213 - 1239
  • [50] Unreinforced masonry walls with irregular opening layouts: reliability of equivalent-frame modelling for seismic vulnerability assessment
    Berti, Manuel
    Salvatori, Luca
    Orlando, Maurizio
    Spinelli, Paolo
    BULLETIN OF EARTHQUAKE ENGINEERING, 2017, 15 (03) : 1213 - 1239
12345