Thermal-aware 3D multi-core processor design using core and level-2 cache placement

被引：0
|
作者：
Son, Dong Oh [1 ]
Choi, Hong Jun [1 ]
Jeon, Hyung Gyu [1 ]
Kim, Cheol Hong [1 ]
机构：
[1] School of Electronics and Computer Engineering, Chonnam National University, Gwangju, 500-757, Korea, Republic of
来源：
International Journal of Control and Automation | 2013年 / 6卷 / 01期
关键词：
3D architectures - Floorplans - Integration density - Interconnection delay - Lower-power consumption - Multi-core processor - Multicore architectures - Temperature behavior;
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页码：25 / 32
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