An optimization algorithm for minimizing crosstalk in VLSI circuit's physical design

被引:0
|
作者
Zhang, X. [1 ]
Zhao, M. [1 ]
Fan, M. [1 ]
Li, C.-H. [1 ]
Yu, J.-B. [1 ]
Huang, J. [1 ]
机构
[1] Information Center, Univ. Electron. Sci. Technol. China, Chengdu 610054, China
关键词
D O I
暂无
中图分类号
学科分类号
摘要
7
引用
收藏
页码:289 / 293
相关论文
共 50 条
  • [21] Efficient parametric yield optimization of VLSI circuit by uniform design sampling method
    Jing, ME
    Hao, Y
    Zhang, JF
    Ma, PJ
    MICROELECTRONICS RELIABILITY, 2005, 45 (01) : 155 - 162
  • [22] TIMING AND AREA OPTIMIZATION FOR STANDARD-CELL VLSI CIRCUIT-DESIGN
    CHUANG, WT
    SAPATNEKAR, SS
    HAJJ, IN
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1995, 14 (03) : 308 - 320
  • [23] Reordering Algorithm for Minimizing Test Power in VLSI Circuits
    Paramasivam, K.
    Gunavathi, K.
    ENGINEERING LETTERS, 2007, 14 (01)
  • [24] PHYSICAL INTUITION AND VLSI PHYSICAL DESIGN
    LINSKER, R
    AIP CONFERENCE PROCEEDINGS, 1984, (122) : 251 - 260
  • [25] Application of an EACS algorithm to obstacle detour routing in VLSI physical design
    Li, J
    Liu, HZ
    Yang, B
    Yu, JB
    Xu, N
    Li, CH
    2003 INTERNATIONAL CONFERENCE ON MACHINE LEARNING AND CYBERNETICS, VOLS 1-5, PROCEEDINGS, 2003, : 1553 - 1558
  • [26] Ant Colony Optimization Based Partition Model for VLSI Physical Design
    Guru, Pavithra R.
    Vaithianathan, V.
    2020 INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND INFORMATICS (ICCCI - 2020), 2020, : 105 - 109
  • [27] An eincient optimization algorithm in integrated circuit reliability design
    Liu, HX
    Hao, Y
    Sun, Z
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2003, 18 (12) : 1024 - 1029
  • [28] VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm
    Kuan, Ta-Wen
    Wang, Jhing-Fa
    Wang, Jia-Ching
    Lin, Po-Chuan
    Gu, Gaung-Hui
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (04) : 673 - 683
  • [29] Estimation of Crosstalk Noise for RLC Interconnects in Deep Submicron VLSI Circuit
    Maniruzzaman, Md.
    Ahmed, Shakil
    Fattah, Galib Md.
    Toma, Rafia Nishat
    2ND INTERNATIONAL CONFERENCE ON ELECTRICAL ENGINEERING AND INFORMATION COMMUNICATION TECHNOLOGY (ICEEICT 2015), 2015,
  • [30] Adaptive genetic algorithm for VLSI circuit partitioning
    Democritus Univ of Thrace, Xanthi, Greece
    Int J Electron, 2 (205-214):