Architecting the future

被引:0
|
作者
Arora, Narain [1 ]
机构
[1] Cadence Design Systems
来源
New Electronics | 2004年 / 37卷 / 10期
关键词
Capacitance - Costs - Dielectric materials - Electric resistance - Inductance - Magnetic susceptibility - Product design - Production engineering - Quality control - Reliability - Surface topography;
D O I
暂无
中图分类号
学科分类号
摘要
The features of test chips which are used to validate the X Architecture, an interconnect architecture, are discussed. The chips are used to achieve accurate modeling and characterization of interconnect wires and to ensure data accuracy for the expensive mask sets required for new generation devices. The chips are important for design for manufacturability (DFM), as they enable chipmakers to verify the quality and reliability of design rules prior to mass production. X Architecture test chips aims to optimize minimum allowable width and spacing rules for diagonal wiring, to compare wire resistance and inductance values for diagonal and orthogonal lines and to study optical proximity correction (OPC) effects on diagonal lines.
引用
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页码:29 / 30
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