LACC: a hardware and software co-design accelerator for deep neural networks

With the increasing of data size and model size, deep neural networks (DNNs) show outstanding performance in many artificial intelligence (AI) applications. But the big model size makes it a challenge for high-performance and low-power running DNN on processors, such as central processing unit (CPU), graphics processing unit (GPU), and tensor processing unit (TPU). This paper proposes a LOGNN data representation of 8 bits and a hardware and software co-design deep neural network accelerator LACC to meet the challenge. LOGNN data representation replaces multiply operations to add and shift operations in running DNN. LACC accelerator achieves higher efficiency than the state-of-the-art DNN accelerators by domain specific arithmetic computing units. Finally, LACC speeds up the performance per watt by 1.5 times, compared to the state-of-the-art DNN accelerators on average. Copyright © by HIGH TECHNOLOGY LETTERS PRESS.