Unified hardware architecture for 2D transform in H.266/VVC

被引：0

作者：

Chen J.-Y. ^{[1
]}

Sun B. ^{[1
]}

Huang X.-F. ^{[2
]}

Sheng Q.-H. ^{[3
]}

Lai C.-C. ^{[3
]}

Jin X.-Y. ^{[1
]}

机构：

[1] Polytechnic Institute, Zhejiang University, Hangzhou

[2] School of Communication Engineering, Hangzhou Dianzi University, Hangzhou

[3] School of Electronics and Information, Hangzhou Dianzi University, Hangzhou

来源：

Zhejiang Daxue Xuebao (Gongxue Ban)/Journal of Zhejiang University (Engineering Science) | 2023年 / 57卷 / 09期

关键词：

application-specific integrated circuit (ASIC); discrete cosine transform (DCT); discrete sine transform (DST); H.266/VVC; hardware architecture; pipeline;

D O I：

10.3785/j.issn.1008-973X.2023.09.021

中图分类号：

学科分类号：

摘要：

A unified hardware architecture was proposed in order to reduce the hardware implementation area and the power of the 2D transform in H.266/VVC. The architecture supported the full-size discrete cosine transform (DCT-II, DCT-VIII) and the discrete sine transform (DST-VII). The architecture consisted of two parallel 1D transform modules and one transpose memory. The 1D transform module was designed based on the multiple constant multiplication (MCM), and a reusable MCM computing unit was designed for all transform types and sizes. The transpose memory was proposed in order to support the pipeline input of the mixed blocks. And the transpose memory was implemented based on static random-access memory (SRAM), used a diagonal storage method with read and write pointers, and used first input first output (FIFO) to cache block information. Experimental results showed that the unified computing unit reduced the area of the transform architecture by 1.3% and the power consumption by 49.5%, and the transpose memory reduced the SRAM storage space by half with the high-frequency zeroing feature of VVC. © 2023 Zhejiang University. All rights reserved.

引用

页码：1894 / 1902

页数：8

共 21 条

[11] DEMPSTER A G, MACLEOD M D., Use of minimum-adder multiplier blocks in FIR digital filters [J], IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 42, 9, pp. 569-577, (1995)
[12] FARHAT I, HAMIDOUCHE W, GRILL A, Et al., Lightweight hardware implementation of VVC transform block for ASIC decoder [C], ICASSP 2020-2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 1663-1667, (2020)
[13] FARHAT I, HAMIDOUCHE W, GRILL A, Et al., Lightweight hardware transform design for the versatile video coding 4K ASIC decoders [J], IEEE Transactions on Consumer Electronics, 67, 4, pp. 329-340, (2021)
[14] MERT A C, KALALI E, HAMZAOGLU I., High performance 2D transform hardware for future video coding [J], IEEE Transactions on Consumer Electronics, 63, 2, pp. 117-125, (2017)
[15] HAO Z J, XU F, XIANG G Q, Et al., A multiplier-less transform architecture with the diagonal data mapping transpose memory for the AVS3 standard [C], 2021 IEEE 14th International Conference on ASIC (ASICON), pp. 1-4, (2021)
[16] HAO Z J, ZHENG Q, FAN Y B, Et al., An area-efficient unified transform architecture for VVC [C], 2022 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2012-2016, (2022)
[17] MEHER P K, PARK S Y, MOHANTY B K, Et al., Efficient [17] integer DCT architectures for HEVC [J], IEEE Transactions on Circuits and Systems for Video Technology, 24, 1, pp. 168-178, (2014)
[18] ZHENG M K, ZHENG J Y, CHEN Z F, Et al., A reconfigurable architecture for discrete cosine transform in video coding [J], IEEE Transactions on Circuits and Systems for Video Technology, 30, 3, pp. 810-821, (2020)
[19] VORONENKO Y, PUSCHEL, Multiplierless multiple constant multiplication, ACM Transactions on Algorithms, 3, 2, (2007)
[20] CHEN W H, SMITH C, FRALICK S., A fast computational algorithm for the discrete cosine transform

← 1 2 3 →