Unified hardware architecture for 2D transform in H.266/VVC

A unified hardware architecture was proposed in order to reduce the hardware implementation area and the power of the 2D transform in H.266/VVC. The architecture supported the full-size discrete cosine transform (DCT-II, DCT-VIII) and the discrete sine transform (DST-VII). The architecture consisted of two parallel 1D transform modules and one transpose memory. The 1D transform module was designed based on the multiple constant multiplication (MCM), and a reusable MCM computing unit was designed for all transform types and sizes. The transpose memory was proposed in order to support the pipeline input of the mixed blocks. And the transpose memory was implemented based on static random-access memory (SRAM), used a diagonal storage method with read and write pointers, and used first input first output (FIFO) to cache block information. Experimental results showed that the unified computing unit reduced the area of the transform architecture by 1.3% and the power consumption by 49.5%, and the transpose memory reduced the SRAM storage space by half with the high-frequency zeroing feature of VVC. © 2023 Zhejiang University. All rights reserved.