Design and Performance Analysis of Gate Overlap Dual Material Tunnel Field Effect Transistor

被引:0
|
作者
Buttol, S. [1 ]
Balaji, B. [1 ]
机构
[1] Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Green Fields, Andhra Pradesh, A.P, Vaddeswaram, India
关键词
Biosensors - Carrier concentration - Dielectric materials - Drain current - Electric fields - Molecules - Surface potential;
D O I
10.5829/IJE.2024.37.09C.07
中图分类号
学科分类号
摘要
This study introduces a biosensor employing a dielectric-modulated dual material gate tunnel field effect transistor (DM-DMG TFET) in 10 nanometer technology. To detect diverse bio molecules, the biosensor incorporates a nano gap cavity formed through gate overlap on the drain side. The variation in ambipolar current serves as the sensing parameter, influenced by altering the dielectric constants of immobilized bio molecules within the nano cavity. In this paper, the simulation results of biosensor employing a dielectric-modulated dual material gate tunnel field effect transistor with different dielectric constants imposed in nano cavity. A comprehensive examination of the biosensor's performance is conducted, exploring various positions and filling factors of bio molecules within the nano cavity region. This analysis involves a thorough investigation into the device's performance, considering a range of parameters such as drain current, electric field distribution, variations in surface potential, configurations of energy bands, behaviors of carrier concentration, and the Ion/Ioff ratio. The simulations are done using the Silvaco TCAD Atlas tool. © 2024 The author(s). This is an open access article distributed under the terms of the Creative Commons Attribution (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, as long as the original authors and source are cited. No permission is required from the authors or the publishers.
引用
收藏
页码:1773 / 1779
相关论文
共 50 条
  • [31] Design analysis of Gate-All-Around nanowire tunnel field effect transistor
    Sharma, Nitika
    Garg, Nidhi
    Kaur, Gurpreet
    [J]. MATERIALS TODAY-PROCEEDINGS, 2021, 45 : 5308 - 5314
  • [32] Subthreshold Performance Analysis of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel Field Effect Transistor for Ultra Low Power Applications
    Venkatesh, M.
    Suguna, M.
    Balamurugan, N. B.
    [J]. JOURNAL OF ELECTRONIC MATERIALS, 2019, 48 (10) : 6724 - 6734
  • [33] Subthreshold Performance Analysis of Germanium Source Dual Halo Dual Dielectric Triple Material Surrounding Gate Tunnel Field Effect Transistor for Ultra Low Power Applications
    M. Venkatesh
    M. Suguna
    N. B. Balamurugan
    [J]. Journal of Electronic Materials, 2019, 48 : 6724 - 6734
  • [34] Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor
    Ahish, S.
    Sharma, Dheeraj
    Vasantha, M. H.
    Kumar, Y. B. N.
    [J]. SUPERLATTICES AND MICROSTRUCTURES, 2017, 103 : 93 - 101
  • [35] Characteristic Analysis of Triple Material Tri-Gate Junctionless Tunnel Field Effect Transistor
    Dewan, Monzurul Islam
    Bin Kashem, Md. Tashfiq
    Subrina, Samia
    [J]. 2016 9TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (ICECE), 2016, : 333 - 336
  • [36] The Effect of a Dual Oxide - Dual Gate Material and a Sensitivity Analysis on the Performance of a Junctionless Tunnel FET
    Koppolu, Kalpana
    Samuyelu, B.
    Rao, C. B. K.
    [J]. SILICON, 2024, 16 (09) : 3905 - 3915
  • [37] Impact of gate leakage considerations in tunnel field effect transistor design
    Chaturvedi, Poornendu
    Kumar, M. Jagadesh
    [J]. JAPANESE JOURNAL OF APPLIED PHYSICS, 2014, 53 (07)
  • [38] An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications
    Samuel, T. S. Arun
    Balamurugan, N. B.
    [J]. JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY, 2014, 9 (01) : 247 - 253
  • [39] Characterization and modeling of dual material double gate tunnel field effect transistor using superposition approximation method
    Jossy, A. Maria
    Vigneswaran, T.
    Malarvizhi, S.
    Nagarajan, K. K.
    [J]. CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2019, 31 (14):
  • [40] Analog performance of double gate junctionless tunnel field effect transistor
    M.W.Akram
    Bahniman Ghosh
    [J]. Journal of Semiconductors, 2014, (07) : 41 - 45