Research on the Parallel Tractability of Knowledge Graph Reasoning based on Boolean Circuits

Although neural methods have been comprehensively applied in different fields, symbolic based logic reasoning is still the main choice for numerous applications based on knowledge graphs. To enhance the efficiency of knowledge graph reasoning, researchers studied how to design parallel algorithms for reasoning, and take advantage of high-performance architectures, like neural networks. Although parallel algorithms and architectures improve the performance of reasoning to some degree, the task of reasoning is essentially bounded by its computational complexity, i.e., the PTiMe-Completeness or higher complexities. This means that the task of reasoning is not parallelly tractable. In this work, we investigate the parallel tractability of knowledge graph reasoning from the perspective of parallel complexity. We concentrate on knowledge graphs that are Datalog rewritable. We aim to capture the parallelly tractable classes of knowledge graphs, for which, the task of reasoning falls in the NC complexity. To this end, we employ the computational model of Boolean circuit to formalize knowledge graph reasoning and further obtain all the theoretical results. We then use the results to analyze DHL（Description Horn Logic）, a fragment of description logic. We give the properties that ensure the parallel tractability of DHL reasoning. One can utilize our results to check the parallel tractability of real knowledge graphs. In addition, the Boolean circuits proposed in this paper can also be used to construct neural networks to perform knowledge graph reasoning.