A low power, low noise figure quadrature demodulator for a 60GHz receiver in 65-nm CMOS technology

This paper presents tne design of a low power(LP) and a low noise figure(NF) quadrature demodulator with an on-chip frequency divider for quadrature local oscillator(LO) signal generation.The transconductance stage of the mixer is implemented by an AC-coupled self-bias current reuse topology.On-chip series inductors are employed at the gate terminals of the differential input transconductance stage to improve the voltage gain by enhancing the effective transconductance.The chip is implemented in 65-nm LP CMOS technology.The demodulator is designed for an input radio frequency(RF) band ranging from 10.25 to 13.75 GHz.A fixed LO frequency of 12 GHz down-converts the RF band to an intermediate frequency(IF) band ranging from DC to 1.75 GHz.From10 MHz to 1.75 GHz the demodulator achieves a voltage conversion gain(VCG) ranging from 14.2 to 13.2 dB,and a minimum single-sideband NF(SSB-NF) of 9 dB.The measured third-order input intercept point(IIP3) is—3.3 dBm for a two-tone test frequency spacing of 1 MHz.The mixer alone draws a current of only 2.5 mA,whereas the complete demodulator draws a current of 7.18 mA from a 1.2 V supply.The measurement results for a frequency divider,which was fabricated individually,prior to being integrated with the quadrature demodulator,in 65-nm LP CMOS technology,are also presented in this paper.