NeuroREC: A 28-nm Efficient Neuromorphic Processor for Radar Emitter Classification

被引:0
|
作者
Wang, Zilin [1 ]
Ou, Zehong [2 ]
Zhong, Yi [1 ]
Yang, Youming [1 ]
Lun, Li [1 ]
Li, Hufei [2 ]
Cao, Jian [2 ]
Cui, Xiaoxin [1 ]
Jia, Song [1 ]
Wang, Yuan [1 ,3 ,4 ]
机构
[1] Peking Univ, MPW Ctr, Sch Integrated Circuits, Key Lab Microelect Devices & Circuits, Beijing 100871, Peoples R China
[2] Peking Univ, Sch Software & Microelect, Beijing 102600, Peoples R China
[3] Beijing Lab Future Integrated Circuit Technol & Sc, Beijing 100871, Peoples R China
[4] Beijing Adv Innovat Ctr Integrated Circuits, Beijing 100871, Peoples R China
关键词
Radar; Accuracy; Energy efficiency; Indexes; Biological system modeling; System-on-chip; Power demand; Radar emitter classification; spiking neural network; neuromorphic computing; weight compression; ON-CHIP; SYSTEM; MODELS; MEMORY;
D O I
10.1109/TCSI.2024.3427385
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Radar emitter classification (REC) plays an important role in modern warfare. Traditional REC methods have difficulty identifying complex radar signals in the present day. Inspired by biology, spiking neural networks (SNNs) have gradually gained widespread attention due to their low power characteristics. Compared with convolutional neural networks (CNNs), SNNs are more suitable for application in the field of REC. The reason is that SNN can not only maintain higher accuracy in the presence of noise interference, but also reduce the power consumption of mobile devices. However, it is challenging to make full use of the input sparsity of radar emitter signals and the weight sparsity of pruned SNN models. In this paper, a 28-nm neuromorphic processor for REC named NeuroREC is proposed. It uses matrix compression algorithms to store sparse weights on chip, and designs corresponding spike detection circuits for this purpose. As a single-core design, we propose a ping-pong running mechanism to alleviate the imbalance between IO throughput and peak performance. Two SNN models for classifying RadioML2016.b and RadioML2018.a datasets are deployed on the chip, achieving competitive accuracy with only 8 timesteps, and demonstrating better robustness than CNN. Fabricated in 28-nm CMOS process, NeuroREC runs at frequencies ranging from 22.5MHz to 744MHz. Under specific sparsity conditions, it can reach an energy efficiency of 7.22TSOP/W for 8-bit weight.
引用
收藏
页码:6215 / 6228
页数:14
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