A ROM-Less DDS with High-Speed Selectors for Reduction in DAC Settling Time Requirements

被引:1
|
作者
Shibue, Haruki [1 ]
Nosaka, Hideyuki [1 ]
机构
[1] Ritsumeikan Univ, Dept Elect & Elect Engn, Kyoto, Japan
来源
2024 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM, IMS 2024 | 2024年
关键词
local oscillator; frequency synthesizer; direct digital synthesizer; interpolation; jitter; DIRECT DIGITAL SYNTHESIZER;
D O I
10.1109/IMS40175.2024.10600259
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a new phase interpolation direct digital synthesizer (DDS) for reduction in digital-to-analog converter (DAC) performance requirements. The phase interpolator makes the accumulator overflow pulses line up at exactly equal intervals, so the DDS can output a square wave with high frequency purity. The newly proposed two-step integrator generates two-step ramp waves by combining highspeed selectors and DACs. Therefore, the requirement for highspeed settling time for the DAC, which was required in the conventional phase interpolation type DDS, is relaxed. As a result, the proposed DDS can achieve low power consumption, high-speed operation, and improved output frequency purity. The measured spurious free dynamic range of prototype DDS output is 53.7 dBc.
引用
收藏
页码:796 / 799
页数:4
相关论文
共 26 条
  • [21] A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DWA
    Jo, Jun-Gi
    Noh, Jinho
    Yoo, Changsik
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (11) : 2469 - 2477
  • [22] Eddy Current Reduction in High-Speed Machines and Eddy Current Loss Analysis With Multislice Time-Stepping Finite-Element Method
    Niu, Shuangxia
    Ho, S. L.
    Fu, W. N.
    Zhu, Jianguo
    IEEE TRANSACTIONS ON MAGNETICS, 2012, 48 (02) : 1007 - 1010
  • [23] A New High-Speed Droplet-Real-Time Polymerase Chain Reaction Method Can Detect Bovine Respiratory Syncytial Virus in Less than 10 Min
    Uehara, Masayuki
    Matsuda, Kazuyuki
    Sugano, Mitsutoshi
    Honda, Takayuki
    JOURNAL OF VETERINARY MEDICAL SCIENCE, 2014, 76 (03): : 477 - 480
  • [24] Analysis and Design of Crosstalk Noise Reduction for Coupled Striplines Inserted Guard Trace with an Open-Stub on Time-Domain in High-Speed Digital Circuits
    Shiue, Guang-Hwa
    Shiu, Jia-Hung
    Chiu, Po-Wei
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (10): : 1573 - 1582
  • [25] A recovery algorithm of linear complexity in the time-domain layered finite element reduction recovery (LAFE-RR) method for large scale electromagnetic analysis of high-speed ICs
    Gan, Houle
    Jiao, Dan
    ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2007, : 287 - +
  • [26] A recovery algorithm of linear complexity in the time-domain layered finite element reduction recovery (LAFE-RR) method for large-scale electromagnetic analysis of high-speed ICs
    Gan, Houle
    Jiao, Dan
    IEEE TRANSACTIONS ON ADVANCED PACKAGING, 2008, 31 (03): : 612 - 618