A ROM-Less DDS with High-Speed Selectors for Reduction in DAC Settling Time Requirements

被引:1
|
作者
Shibue, Haruki [1 ]
Nosaka, Hideyuki [1 ]
机构
[1] Ritsumeikan Univ, Dept Elect & Elect Engn, Kyoto, Japan
来源
2024 IEEE/MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM, IMS 2024 | 2024年
关键词
local oscillator; frequency synthesizer; direct digital synthesizer; interpolation; jitter; DIRECT DIGITAL SYNTHESIZER;
D O I
10.1109/IMS40175.2024.10600259
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a new phase interpolation direct digital synthesizer (DDS) for reduction in digital-to-analog converter (DAC) performance requirements. The phase interpolator makes the accumulator overflow pulses line up at exactly equal intervals, so the DDS can output a square wave with high frequency purity. The newly proposed two-step integrator generates two-step ramp waves by combining highspeed selectors and DACs. Therefore, the requirement for highspeed settling time for the DAC, which was required in the conventional phase interpolation type DDS, is relaxed. As a result, the proposed DDS can achieve low power consumption, high-speed operation, and improved output frequency purity. The measured spurious free dynamic range of prototype DDS output is 53.7 dBc.
引用
收藏
页码:796 / 799
页数:4
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