A Comparative Study of HBL and VBL 3D DRAM: Signal Margin, Bit-cell Density, and Scalability

Ongoing evolution of DRAM scaling can be enabled by monolithically stacking DRAM cells in the vertical direction (3D DRAM). However, there is no consensus as to whether 3D DRAM with horizontal bitline (HBL) or vertical bitline (VBL) is more scalable. Here we evaluate the signal margin and bitcell density of horizontal bitline (HBL) vs. vertical bitline (VBL) 3D DRAM using Coventor process model and circuit simulation. We show that VBL has 37% smaller BL-BL coupling noise and 2x higher iso-density signal margin than HBL at 64 layers. To surpass the density of 12 nm 4F2 DRAM while maintaining robust signal margin, VBL 3D DRAM requires similar to 50 layers, which is 35% fewer than HBL.