P-GaN Gate HEMTs: A Solution to Improve the High-Temperature Gate Lifetime

被引:0
|
作者
Tallarico, A. N. [1 ]
Millesimo, M. [1 ]
Borga, M. [2 ]
Bakeroot, B. [3 ,4 ]
Posthuma, N. [2 ]
Cosnier, T.
Decoutere, S. [2 ]
Sangiorgi, E. [1 ]
Fiegna, C. [1 ]
机构
[1] Univ Bologna, Adv Res Ctr Elect Syst, Dept Elect Elect & Informat Engn, I-47522 Cesena, Italy
[2] Imec, B-3001 Leuven, Belgium
[3] IMEC, Ctr Microsyst Technol, B-9052 Ghent, Belgium
[4] Univ Ghent, B-9052 Ghent, Belgium
基金
欧盟地平线“2020”;
关键词
Logic gates; Stress; MODFETs; HEMTs; Layout; Electric fields; Electric breakdown; Gallium nitride; reliability; Schottky gate; breakdown; time to failure; gate layout; RELIABILITY; FREQUENCY; BREAKDOWN;
D O I
10.1109/LED.2024.3424563
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this letter, we report an approach to improve the forward bias gate reliability of Schottky gate p-GaN HEMTs. In particular, a gate layout solution, namely Gate Within Active Area (GWA), aimed at improving the high-temperature time to failure (TTF), is proposed and validated. This solution allows to avoid the exposure of the gate finger (p-GaN/metal) to the nitrogen-implantation needed for termination and isolation purposes. GWA devices feature a significantly improved gate reliability at high temperature with respect to the reference ones, under both DC and pulsed stress tests. Finally, it is demonstrated that the Schottky gate p-GaN HEMTs show a positive temperature-dependent gate TTF in a range up to 150 degrees C, confirming the crucial role of impact ionization on the gate failure.
引用
收藏
页码:1630 / 1633
页数:4
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