Design Points of InGaAs MFMIS Tunnel FET for Large Memory Window and Stable Ferroelectric Memory Operation

被引:0
|
作者
Ko, Kyul [1 ,2 ]
Ahn, Dae-Hwan [3 ]
Jeong, Jai-Youn [1 ]
Ju, Byeong-Kwon [2 ]
Han, Jae-Hoon [1 ]
机构
[1] Korea Inst Sci & Technol KIST, Ctr Optoelect Mat & Devices, Seoul 02792, South Korea
[2] Korea Univ, Sch Elect Engn, Display & Nanosensor Lab, Seoul 02841, South Korea
[3] Korea Inst Sci & Technol KIST, Ctr Quantum Informat, Seoul 02792, South Korea
基金
新加坡国家研究基金会;
关键词
Iron; Indium gallium arsenide; TFETs; Capacitors; MOSFET; Logic gates; Hafnium oxide; Ferroelectric (FE) FET; Hf0.5Zr0.5O2(HZO); InGaAs; metal-ferroelectric-metal-insulator-semiconductor (MFMIS); tunnel FET; TRANSISTORS; FUTURE;
D O I
10.1109/TED.2024.3449255
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We study device structures and their design points of HfZrO X -based InGaAs metal-ferroelectric-metal-insulator-semiconductor (MFMIS) ferroelectric tunnel FETs (Fe-TFETs) based on ferroelectric (FE) polarization-controlled band-to-band tunneling (BTBT) for stable nonvolatile memory (NVM) operation. We monolithically integrated a HfZrO X MFM capacitor into the baseline tunnel field-effect transistor (TFET), which has steep subthreshold swing (SS) characteristics of sub-60 mV/decade with a HfO2 /Al2O3 gate-stack, compared to the reference MOSFET. We found temperature-stable NVM behaviors of the InGaAs Fe-TFET compared to the InGaAs ferroelectric MOSFETs (Fe-MOSFETs) at the measurement temperature range from - 20 C-degrees to 85 C-degrees. Furthermore, we explored the scaling effects of the MFMIS structure using a high- kappa HfO2 gate insulator layer to pursue a steep SS, and a large capacitance ratio between the dielectric (DE) and FE capacitors. The InGaAs MFMIS-structure Fe-TFET achieves stable retention over 10(4) s and excellent endurance during 10 6 cycles at the DE/FE capacitance ratio of 27.5.
引用
收藏
页码:6435 / 6441
页数:7
相关论文
共 50 条
  • [1] Strategies for a Wide Memory Window of Ferroelectric FET for Multilevel Ferroelectric VNAND Operation
    Myeong, Ilho
    Kim, Hyoseok
    Kim, Seunghyun
    Lim, Suhwan
    Kim, Kwangsu
    Kim, Wanki
    Ha, Daewon
    Ahn, Sujin
    Song, Jaihyuk
    IEEE ELECTRON DEVICE LETTERS, 2024, 45 (07) : 1185 - 1188
  • [2] Laminated Ferroelectric FET With Large Memory Window and High Reliability
    Lee, Hyun Jae
    Nam, Seunggeol
    Lee, Yunseong
    Kim, Kihong
    Choe, Duk-Hyun
    Yoo, Sijung
    Park, Yoonsang
    Jo, Sanghyun
    Kim, Donghoon
    Heo, Jinseong
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (04) : 2411 - 2416
  • [3] Impact of Domain Wall Motion on the Memory Window in a Multidomain Ferroelectric FET
    Pandey, Nilesh
    Chauhan, Yogesh Singh
    IEEE ELECTRON DEVICE LETTERS, 2022, 43 (11) : 1854 - 1857
  • [4] Circular ferroelectric tunnel junctions for the improvement of memory window and endurance
    Kim, Dong-Oh
    Kim, Changha
    Kim, Hyun-Min
    Park, Jonghyuk
    Jeon, Bosung
    Kwon, Daewoong
    Choi, Woo Young
    JAPANESE JOURNAL OF APPLIED PHYSICS, 2023, 62 (SG)
  • [5] Design Optimization of Tunnel FET for Dynamic Memory Applications
    Navlakha, Nupur
    Lin, Jyi-Tsong
    Kranti, Abhinav
    2017 INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS (EDSSC), 2017,
  • [6] Multi-Level Operation of Ferroelectric FET Memory Arrays for Compute-In-Memory Applications
    Mueller, Franz
    De, Sourav
    Lederer, Maximilian
    Hoffmann, Raik
    Olivo, Ricardo
    Kaempfe, Thomas
    Seidel, Konrad
    Ali, Tarek
    Mulaosmanovic, Halid
    Duenkel, Stefan
    Mueller, Johannes
    Beyer, Sven
    Gerlach, Gerald
    2023 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW, 2023, : 149 - 152
  • [7] Embedding security into ferroelectric FET array via in situ memory operation
    Xu, Yixin
    Xiao, Yi
    Zhao, Zijian
    Muller, Franz
    Vardar, Alptekin
    Gong, Xiao
    George, Sumitha
    Kampfe, Thomas
    Narayanan, Vijaykrishnan
    Ni, Kai
    NATURE COMMUNICATIONS, 2023, 14 (01)
  • [8] Embedding security into ferroelectric FET array via in situ memory operation
    Yixin Xu
    Yi Xiao
    Zijian Zhao
    Franz Müller
    Alptekin Vardar
    Xiao Gong
    Sumitha George
    Thomas Kämpfe
    Vijaykrishnan Narayanan
    Kai Ni
    Nature Communications, 14
  • [9] Understanding the Memory Window of Ferroelectric FET and Demonstration of 4.8-V Memory Window With 20-nm HfO2
    Qin, Yixin
    Zhao, Zijian
    Lim, Suhwan
    Kim, Kijoon
    Kim, Kwangsoo
    Kim, Wanki
    Ha, Daewon
    Narayanan, Vijaykrishnan
    Ni, Kai
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2024, 71 (08) : 4655 - 4663
  • [10] Stacked HZO/α-In2Se3 Ferroelectric Dielectric/Semiconductor FET With Ultrahigh Speed and Large Memory Window
    Huo, Jiali
    Zhang, Zhaohao
    Zhang, Yadong
    Zhang, Fan
    Yan, Gangping
    Tian, Guoliang
    Xu, Haoqing
    Zhan, Guohui
    Xu, Gaobo
    Zhang, Qingzhu
    Yin, Huaxiang
    Wu, Zhenhua
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2023, 70 (06) : 3071 - 3075