Securing the IoT ecosystem: ASIC-based hardware realization of Ascon lightweight cipher

被引:4
|
作者
Khan, Safiullah [1 ]
Inayat, Kashif [2 ,3 ]
Bin Muslim, Fahad [4 ]
Shah, Yasir Ali [5 ]
Rehman, Muhammad Atif Ur [1 ]
Khalid, Ayesha [6 ]
Imran, Malik [6 ]
Abdusalomov, Akmalbek [7 ,8 ]
机构
[1] Manchester Metropolitan Univ, Dept Comp & Math, Manchester M15 6BX, England
[2] Incheon Natl Univ, Dept Elect Engn, Syst Chips Lab, Incheon 22012, South Korea
[3] Ctr Nacl Supercomputac, Barcelona Supercomp Ctr, Barcelona, Spain
[4] GIK Inst, Fac Comp Sci & Engn, Swabi 23460, Pakistan
[5] Ulster Univ, Sch Comp Engn & Intelligent Syst, Magee Campus, Londonderry BT48 7JL, North Ireland
[6] Queens Univ Belfast, Ctr Secure Informat Technol CSIT, Belfast BT7 1NN, North Ireland
[7] Gachon Univ, Dept Comp Engn, Seongnam 461701, South Korea
[8] Tashkent State Univ Econ, Dept Informat Syst & Technol, Tashkent 100066, Uzbekistan
关键词
Internet of Things; Lightweight cryptography; Ascon; ASIC implementations;
D O I
10.1007/s10207-024-00904-1
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The Internet of Things (IoT) nodes consist of sensors that collect environmental data and then perform data exchange with surrounding nodes and gateways. Cybersecurity attacks pose a threat to the data security that is being transmitted in any IoT network. Cryptographic primitives are widely adopted to address these threats; however, the substantial computation demands limit their applicability in the IoT ecosystem. In addition, each IoT node varies with respect to the area and throughput (TP) requirements, thus demanding flexible implementation for encryption/decryption processes. To solve these issues, this work implements the NIST lightweight cryptography standard, Ascon, on a SAED 32 nm process design kit (PDK) library by employing loop folded, loop unrolled and fully unrolled architectures. The fully unrolled architecture can achieve the highest TP but at the cost of higher area utilisation. Unrolling by a lower factor results in lower area implementations, enabling the exploration of design space to tackle the trade-off between area and TP performance of the design. The implementation results show that, for loop folded architecture, Ascon-128 and Ascon-128a require 36.7k mu m2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu \textrm{m}<^>{2}$$\end{document} and 38.5k mu m2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu \textrm{m}<^>{2}$$\end{document} chip area, respectively compared to 277.1k mu m2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu \textrm{m}<^>{2}$$\end{document} and 306.6k mu m2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu \textrm{m}<^>{2}$$\end{document} required by their fully unrolled implementations. The proposed implementation strategies can adjust the number of rounds to accommodate the varied requirements of IoT ecosystems. An implementation with an open-source 45 nm PDK library is also undertaken for enhanced generalization and reproducibility of the results.
引用
收藏
页码:3653 / 3664
页数:12
相关论文
共 40 条
  • [1] ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications
    Nguyen, Khai-Duy
    Dang, Tuan-Kiet
    Kieu-Do-Nguyen, Binh
    Le, Duc-Hung
    Pham, Cong-Kha
    Hoang, Trong-Thuc
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2025, 72 (01) : 278 - 282
  • [2] Hardware Constructions for Error Detection in Lightweight Authenticated Cipher ASCON Benchmarked on FPGA
    Kaur, Jasmin
    Kermani, Mehran Mozaffari
    Azarderakhsh, Reza
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (04) : 2276 - 2280
  • [3] An ASIC-based capacitance meter: Principle, realization and experiments
    Grisel, R
    Gallorini, R
    Abouchi, N
    IECON-2002: PROCEEDINGS OF THE 2002 28TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, VOLS 1-4, 2002, : 2803 - 2807
  • [4] Homomorphic additive lightweight block cipher scheme for securing IoT applications
    Hariss, Khalil
    Noura, Hassan
    JOURNAL OF INFORMATION SECURITY AND APPLICATIONS, 2023, 76
  • [5] Securing industrial control systems: Developing a SCADA/IoT test bench and evaluating lightweight cipher performance on hardware simulator
    Upadhyay, Darshana
    Ghosh, Sagarika
    Ohno, Hiroyuki
    Zaman, Marzia
    Sampalli, Srinivas
    INTERNATIONAL JOURNAL OF CRITICAL INFRASTRUCTURE PROTECTION, 2024, 47
  • [6] ASIC and FPGA Comparative Study for IoT Lightweight Hardware Security Algorithms
    Samir, Nagham
    Hussein, Abdelrahman Sobeih
    Khaled, Mohaned
    El-Zeiny, Ahmed N.
    Osama, Mahetab
    Yassin, Heba
    Abdelbaky, Ali
    Mahmoud, Omar
    Shawky, Ahmed
    Mostafa, Hassan
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2019, 28 (12)
  • [7] Securing IoT Communications: A Novel Lightweight Stream Cipher Using DNA Cryptography and Grain-80 Cipher
    Mohammad Ubaidullah Bokhari
    Shahnwaz Afzal
    Imran Khan
    Mohd Zain Khan
    SN Computer Science, 6 (2)
  • [8] Hardware realization of a lightweight 2D cellular automata-based cipher for image encryption
    Torres-Huitzil, Cesar
    2013 IEEE 4TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS), 2013,
  • [9] A comprehensive latency profiling study of the Tofino P4 programmable ASIC-based hardware
    Franco, David
    Zaballa, Eder Ollora
    Zang, Mingyuan
    Atutxa, Asier
    Sasiain, Jorge
    Pruski, Aleksander
    Rojas, Elisa
    Higuero, Marivi
    Jacob, Eduardo
    COMPUTER COMMUNICATIONS, 2024, 218 : 14 - 30
  • [10] Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-based DNN Accelerators
    Manasi, Susmita Dey
    Banerjee, Suvadeep
    Davare, Abhijit
    Sorokin, Anton A.
    Burns, Steven M.
    Kirkpatrick, Desmond A.
    Sapatnekar, Sachin S.
    2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC, 2023, : 475 - 482