Microstructure and reflectance of porous GaN distributed Bragg reflectors on silicon substrates

Distributed Bragg reflectors (DBRs) based on alternating layers of porous and non-porous GaN have previously been fabricated at the wafer-scale in heteroepitaxial GaN layers grown on sapphire substrates. Porosification is achieved via the electrochemical etching of highly Si-doped layers, and the etchant accesses the n(+)-GaN layers through nanoscale channels arising at threading dislocations that are ubiquitous in the heteroepitaxial growth process. Here, we show that the same process applies to GaN multilayer structures grown on silicon substrates. The reflectance of the resulting DBRs depends on the voltage at which the porosification process is carried out. Etching at higher voltages yields higher porosities. However, while an increase in porosity is theoretically expected to lead to peak reflectance, in practice, the highest reflectance is achieved at a moderate etching voltage because etching at higher voltages leads to pore formation in the nominally non-porous layers, pore coarsening in the porous layers, and in the worst cases layer collapse. We also find that at the high threading dislocation densities present in these samples, not all dislocations participate in the etching process at low and moderate etching voltages. However, the number of dislocations involved in the process increases with etching voltage.