Area-efficient ultra-wide-tuning-range ring oscillators in 65-nm complementary metal-oxide-semiconductor

In this paper, to analyze the tuning range (TR) of transistors, we introduced two streamlined modeling approaches that can precisely predict the extent and direction of the TR. The first approach, known as the average DC (Id) method, employed a simplified circuit model to dissect transistor characteristics, enabling us to understand the general trajectory of the TR. The second approach involved the transient current Id (tc) method, which offers a nuanced portrayal of the transistor's real-world performance. By analyzing the current fluctuations within the transistor during transient states, its tuning capabilities could be more accurately ascertained. Further, this paper presents several designs for ultra-wide-tuning-range complementary metal-oxide-semiconductor (CMOS) voltage-controlled oscillators (VCOs) that employ a novel two-mode current-starved delay cell, featuring a tunable transistor-based current source for coarse frequency adjustment operating in synergy with a varactor for precise tuning. Using the 65-nm CMOS process, three prototype VCOs (Designs 2/3/4) based on the new cell and targeting different numbers of phases and performance were fabricated, thoroughly characterized, and compared with their traditional inverter-based counterpart (Design 1). Design 1 featured an inverter-based four-phase structure, with an output frequency range of 3.14-9.82 GHz, i.e., a radio frequency (RF) TR of 103%, with phase noise (PN) ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm2. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14-9.17, 1.26-16.53, and 1.15-18.32 GHz, respectively, resulting in increased RF TRs of 155.8%, 171.7% and 176.4%, as well as PN at an offset of 100 MHz in the ranges of 142.1-138, 130.5-131.3, and 131.9-129.6 dBc/Hz, respectively. This yielded better FoMTAs in the ranges of 201.2-209.9, 205.3-217.9, and 194.1-209.9 dBc/Hz, thus allowing the VCOs to maintain consistent performance across the frequency band and occupy comparable or smaller silicon areas of 0.00425, 0.000972, and 0.00348 mm2 in the same 65 nm technology. These designs showcase the versatility and efficiency of the two-mode current-starved delay architecture, which offers wide TRs, tiny areas, and competitive performance metrics for various applications in RF integrated circuits. FIGURE 1. Comparison between the proposed method and prior state-of-the-art: (a) TR vs. frequency; (b) FOMT vs. frequency. FIGURE 2. Comparison between the proposed method and prior art: (a) FOMTA vs. frequency; (b) TR vs. area. These designs showcase the versatility and efficiency of the two-mode current-starved delay architecture, which offers wide tuning ranges, tiny areas, and competitive performance metrics for various applications in RF integrated circuits. Design 1 featured an inverter-based four-phase structure, with an output frequency range of 3.14-9.82 GHz, i.e., an RF tuning range of 103%, with phase noise ranging from 137.7 to 132.1 dBc/Hz at an offset of 100 MHz, figure of merit with tuning range and area (FoMTA) varying from 200.7 to 205.1 dBc/Hz, and area of 0.0036 mm2. In contrast, Designs 2/3/4, based on the new delay cell, featured 8/3/4 phases, with output frequencies in the ranges of 1.14-9.17, 1.26-16.53, and 1.15-18.32 GHz, respectively, resulting in increased RF tuning ranges of 155.8%, 171.7% and 176.4%, as well as phase noise at an offset of 100 MHz in the ranges of 142.1-138, 130.5-131.3, and 131.9-129.6 dBc/Hz, respectively. This yielded better FoMTAs in the ranges of 201.2-209.9, 205.3-217.9, and 194.1-209.9 dBc/Hz, thus allowing the VCOs to maintain consistent performance across the frequency band and occupy comparable or smaller silicon areas of 0.00425, 0.000972, and 0.00348 mm2 in the same 65 nm technology.image