Improving the Efficiency of Software-Based Fault Protection Mechanisms With HUSTLE

To achieve confidence in safety-critical systems, requires among others to meet high requirements on online testing of computer systems, as dictated by safety standards such as ISO26262, IEC61508, and CENELEC EN 5012X. Online testing can be performed through the periodic execution of online SW Test Libraries, which are widely used in safety-related applications as a valuable safety mechanism to protect against random HW faults. SW Test Libraries introduce a non-negligible overhead on system performance, exacerbated by the increasing complexity of HW devices. This contrasts with the efforts of researchers and system designers for developing efficient systems. Reducing this overhead is an important achievement. We propose here HUSTLE, a Hardware Unit for SW-Test Libraries Efficient execution, which can be integrated into the chip design with minimum modification to the CPU's design. HUSTLE contains an Internal Memory, where the library code is stored, and sends instructions to the CPU, bypassing the Memory Subsystem. To further improve efficiency, we also propose a scheduling mechanism that allows to exploit the idle time of the CPU's execution unit. To show the efficiency gain in supporting the test libraries execution, we ran some experiments, where a considerable reduction of the overall CPU load was observed. Finally, remarks regarding the limited impact on the area and power consumption are presented.