Band gap and gate dielectric engineered novel Si0.9Ge0.1/InAs junctionless TFET for RFIC applications

被引:1
|
作者
Kumar, Kaushal [1 ]
Kumar, Ajay [2 ]
Kumar, Vinay [1 ]
Jain, Aditya [3 ]
Sharma, Subhash Chander [4 ]
机构
[1] Graphic Era Deemed be Univ, ECE Dept, Dehra Dun, Uttaranchal, India
[2] Jaypee Inst Informat Technol, ECE Dept, Noida, Uttar Pradesh, India
[3] Symbiosis Int Deemed Univ, Symbiosis Inst Technol, Pune, Maharashtra, India
[4] Indian Inst Technol, Roorkee, Uttaranchal, India
来源
ENGINEERING RESEARCH EXPRESS | 2024年 / 6卷 / 03期
关键词
SiGe/InAs; tunneling interface; intrinsic delay; band gap engineering; junction-less TFET; TUNNEL FET; PERFORMANCE; DESIGN;
D O I
10.1088/2631-8695/ad6bea
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
In this study, we present a dual dielectric material gated novel Si0.9Ge0.1/InAs hetero-structure Junctionless TFET (DMG-HJLTFET), in which first time, a novel amalgamation of Si0.9Ge0.1/InAs along with HfO2 and SiO2 is used on the basis of band gap and gate dielectric engineering respectively. Our main goal is to examine the performance of the reported device in terms of radio frequency (RF), linearity, and intermodulation distortion parameters. The reported device's (DMG-HJLTFET) result is compared with latest published articles and conventional Si-JLTFET to show the improvement. Our simulation results reveal that DMG-HJLTFET outperforms Si-JLTFET in several key metrics, such as parasitic capacitance (C-gg, 49% down arrow), maximum oscillation frequency (f(max), 589 times up arrow), gain bandwidth product (GBP, 238.5 times up arrow), intrinsic gain (A(v), 2.24 x 10(2) times up arrow), peak transconductance (g(m), 110 times up arrow), and second-order voltage intercept point (VIP2, 330.2% up arrow). Our findings lead us to the conclusion that DMG-HJLTFET might be a promising substitute for low-power and high-frequency applications.
引用
收藏
页数:16
相关论文
共 20 条
  • [1] Band Gap and Drain Dielectric Pocket Engineered Si0.2Ge0.8/GaAs Junctionless TFET with Dual Dielectric Gate for Ambipolar Suppression and Electrical Performance Enhancement
    Kumar, Kaushal
    Sharma, Subhash Chandra
    SILICON, 2023, 15 (06) : 2663 - 2677
  • [2] Band Gap and Drain Dielectric Pocket Engineered Si0.2Ge0.8/GaAs Junctionless TFET with Dual Dielectric Gate for Ambipolar Suppression and Electrical Performance Enhancement
    Kaushal Kumar
    Subhash Chandra Sharma
    Silicon, 2023, 15 : 2663 - 2677
  • [3] Band gap and gate underlap engineered novel Si0.2Ge0.8/GaAs JLTFET with dual dielectric gate for improved wireless applications
    Kumar, Kaushal
    Kumar, Ajay
    Kumar, Vinay
    Sharma, Subhash Chander
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2023, 166
  • [4] Impact of band gap and gate dielectric engineering on novel Si0.1Ge0.9-GaAs lateral N-type charge plasma based JLTFET
    Kumar, Kaushal
    Sharma, Subhash Chandra
    MICROELECTRONICS JOURNAL, 2022, 130
  • [5] Ambipolarity Suppression of Band Gap and Gate Dielectric Engineered Novel Si0.2Ge0.8/GaAs JLTFET Using Gate Overlap Technique
    Kaushal Kumar
    Ajay Kumar
    Vinay Kumar
    Aditya Jain
    Subhash Chander Sharma
    Silicon, 2023, 15 : 7837 - 7854
  • [6] Ambipolarity Suppression of Band Gap and Gate Dielectric Engineered Novel Si0.2Ge0.8/GaAs JLTFET Using Gate Overlap Technique
    Kumar, Kaushal
    Kumar, Ajay
    Kumar, Vinay
    Jain, Aditya
    Sharma, Subhash Chander
    SILICON, 2023, 15 (18) : 7837 - 7854
  • [7] Electrical performance of InAs/GaAs0.1Sb0.9heterostructure junctionless TFET with dual-material gate and Gaussian-doped source
    Xie, Haiwu
    Liu, Hongxia
    Chen, Shupeng
    Han, Tao
    Wang, Shulong
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY, 2020, 35 (09)
  • [8] Implementation of Band Gap and Gate Oxide Engineering to Improve the Electrical Performance of SiGe/InAs Charged Plasma-Based Junctionless-TFET
    Kaushal Kumar
    Ajay Kumar
    Varun Mishra
    Subhash Chandra Sharma
    Silicon, 2023, 15 : 1303 - 1313
  • [9] Simulation-Based Study of Si/Si0.9Ge0.1/Si Hetero-Channel FinFET for Enhanced Performance in Low-Power Applications
    Ding, Fei
    Wu, Yi-Ting
    Connelly, Daniel
    Zhang, Wenyi
    Liu, Tsu-Jae King
    IEEE ELECTRON DEVICE LETTERS, 2019, 40 (03) : 363 - 366
  • [10] Correction to: Implementation of Band Gap and Gate Oxide Engineering to Improve the Electrical Performance of SiGe/InAs Charged Plasma-based Junctionless-TFET
    Kaushal Kumar
    Ajay Kumar
    Varun Mishra
    Subhash Chandra Sharma
    Silicon, 2023, 15 : 1315 - 1315