Parallel Implementation of a Convolutional Neural Network on an MPSoC

被引：0

作者：

Mourelle, Luiza de Macedo ^{[1
]}

Nedjah, Nadia ^{[2
]}

Cardoso, Alexandre Nietupski ^{[3
]}

机构：

[1] Univ Estado Rio De Janeiro, Fac Engn, Dept Syst Engn & Computat, Rio De Janeiro, Brazil

[2] Univ Estado Rio De Janeiro, Fac Engn, Dept Elect Engn & Telecommun, Rio De Janeiro, Brazil

[3] Univ Estado Rio De Janeiro, Fac Engn, Postgrad Program Elect Engn, Rio De Janeiro, Brazil

来源：

ADVANCES AND TRENDS IN ARTIFICIAL INTELLIGENCE: THEORY AND APPLICATIONS, IEA-AIE 2024 | 2024年 / 14748卷

关键词：

Convolutional Neural Network; Multiprocessor System-on-Chip; Network-on-Chip;

D O I：

10.1007/978-981-97-4677-4_28

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

commonly employed for pattern recognition and classification tasks in image and video-based applications. The architecture of a Convolutional Neural Network typically comprises a sequence of convolutional layers paired with pooling layers, with the final output being classified by a fully connected layer. The role of the convolutional layer is to enable the mapping of distinctive image features, while the pooling layer serves to reduce the dimensionality of matrices and simplify the data. In this research endeavor, we delve into assessing the performance of a parallelized implementation of a Convolutional Neural Network executed on a Multiprocessor System-on-Chip.

引用

页码：335 / 347

页数：13

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