Ultra-Low Sensing-Time and Hardware-Efficient Spectrum Sensor for Data Fusion-Based Cooperative Cognitive-Radio Network

被引:0
|
作者
Singh, Shakti [1 ]
Shrestha, Rahul [1 ]
机构
[1] Indian Inst Technol Mandi, Sch Comp & Elect Engn, Mandi 175075, India
关键词
Sensors; Cognitive radio; Radio frequency; Hardware; Computational complexity; Indexes; Performance evaluation; Application specific integrated circuit (ASIC); complementary metal oxide semiconductor (CMOS); cognitive radio; cooperative spectrum sensing (CSS); digital architecture design; field programmable gate array (FPGA); PIETRA-RICCI; DETECTOR;
D O I
10.1109/TCE.2023.3322831
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes a low-complexity cooperative-spectrum-sensing (CSS) algorithm that delivers optimum reliability for the data fusion-based cognitive radio network. Based on this CSS algorithm, a new hardware-efficient architecture of the cooperative spectrum sensor (CSR) has been presented here that delivers remarkably low sensing-time, which consequently enhances the data-throughput of cognitive radio network. For the proposed CSS-algorithm and CSR-architecture, extensive analysis on optimality, computational complexity, detection performance, scalability and sensing-time have been showcased in this work. In addition, hardware prototype of new CSR has been designed in FPGA platform and its functional validation is performed in the real-world test setup. Furthermore, ASIC synthesis and post-layout simulation of the CSR chip-layout are carried out using 90 nm and 130 nm CMOS technology nodes. Comparison of these implementation results with relevant contributions from the literature showed that the proposed CSR delivers 47.8x shorter sensing-time and 75x better hardware efficiency than the state-of-the-art works.
引用
收藏
页码:216 / 226
页数:11
相关论文
共 33 条