A Two-step Fine-tuning Assisted Layout Sizing Scheme for Analog/RF Circuits

This paper proposes a two-step fine-tuning assisted layout sizing (FALS) scheme with an efficient post-layout sampling feature, the key of which is to reuse abundant and cheap schematic information with Transfer Learning for quickly pruning design space and achieving global optimization. The innovation is that FALS is the first work to integrate the advantages of two-step optimization and high-accuracy modelbased local optimization. The same optimization results can be achieved by FALS with significantly 10x less total run-time than the conventional DE.