An 80MS/s 70.79dB-SNDR 60.7fJ/conv-step Radiation-Tolerant Semi-Time-interleaved Pipelined-SAR ADC

被引:0
|
作者
Li, Zheyi [1 ,2 ]
Berti, Laurent [1 ]
Lin, Qiuyang [1 ]
Zhao, Jinghao [2 ]
Gorbunov, Maxim [1 ]
Thys, Geert [1 ]
Leroux, Paul [2 ]
机构
[1] IMEC, Leuven, Belgium
[2] Katholieke Univ Leuven, Geel, Belgium
关键词
D O I
10.1109/CICC60959.2024.10529093
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页数:2
相关论文
共 7 条
  • [1] An 80 MS/s 70.8 dB-SNDR Radiation-Tolerant Semi-Time-Interleaved Pipelined-SAR ADC for Space Applications
    Li, Zheyi
    Berti, Laurent
    Zhao, Jinghao
    Lin, Qiuyang
    Gorbunov, Maxim
    Wang, Shiwei
    Thys, Geert
    Leroux, Paul
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2025,
  • [2] A 23fJ/conv-step 12b 290MS/s Time Interleaved Pipelined SAR ADC
    Singh, Sameer
    Govindarajan, Madhusudan
    Venkatesh, T. S.
    Evans, William
    Kansal, Ayushi
    Murali, S. S.
    ESSCIRC CONFERENCE 2015 - 41ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE (ESSCIRC), 2015, : 319 - 322
  • [3] A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry
    Han, Haolin
    Ren, Ruili
    Shen, Yi
    Ding, Ruixue
    Liu, Shubin
    Liang, Hongzhi
    MICROELECTRONICS JOURNAL, 2024, 153
  • [4] A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration
    Verma, Deeksha
    Rikan, Behnam S.
    Shehzad, Khuram
    Kim, Sung Jin
    Khan, Danial
    Kommangunta, Venkatesh
    Shah, Syed Adil Ali
    Pu, Younggun
    Yoo, Sang-Sun
    Hwang, Keum Cheol
    Yang, Youngoo
    Lee, Kang-Yoon
    IEEE ACCESS, 2021, 9 : 133143 - 133155
  • [5] A 1.5mW 68dB SNDR 80MS/s 2x Interleaved SAR-Assisted Pipelined ADC in 28nm CMOS
    van der Goes, Frank
    Ward, Chris
    Astgimath, Santosh
    Yan, Han
    Riley, Jeff
    Mulder, Jan
    Wang, Sijia
    Bult, Klaas
    2014 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC), 2014, 57 : 200 - +
  • [6] A 0.7V 12b 160MS/s 12.8fJ/conv-step Pipelined-SAR ADC in 28nm CMOS with Digital Amplifier Technique
    Yoshioka, Kentaro
    Sugimoto, Tomohiko
    Waki, Naoya
    Kim, Sinnyoung
    Kurose, Daisuke
    Ishii, Hirotomo
    Furuta, Masanori
    Sai, Akihide
    Itakura, Tetsuro
    2017 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC), 2017, : 478 - 478
  • [7] A 12-b 1-GS/s 61-dB SNDR Pipelined-SAR ADC With Inverter-Based Residual Amplifier and Tunable Harmonic-Injecting Cross-Coupled-Pair for Distortion Cancelation Achieving 6.3 fJ/conv-step
    Fang, Liang
    Fu, Tao
    Wen, Xianshan
    Gui, Ping
    IEEE SOLID-STATE CIRCUITS LETTERS, 2022, 5 : 194 - 197