Reliability study of fine pitch Cu-Sn micro-bump structure electromigration test by Finite Element Simulation

被引:1
|
作者
Xu, Zheqi [1 ]
Wang, Qian [1 ,2 ]
Tan, Lin [1 ]
Zheng, Kai [3 ]
Zhou, Yikang [3 ]
Cai, Jian [1 ,2 ]
机构
[1] Tsinghua Univ, Sch Integrated Circuits, Beijing, Peoples R China
[2] Beijing Natl Res Ctr Informat Sci & Technol, Beijing, Peoples R China
[3] Semicond Technol Innovat Ctr Beijing Corp, Beijing, Peoples R China
关键词
fine-pitch; micro-bumps; electromigration; AFD; failure mechanism; design rule; SOLDER; FAILURE;
D O I
10.1109/ICEPT59018.2023.10492421
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
As 3D stacking of memory products leads the trend, dimension of micro-bump scales down. General micro-bump pitch has been reduced to 20 similar to 40 mu m, which is almost one order of magnitude smaller than flip chip solder ball. Current density flowing through the micro-bump will increase dramatically under the same supply current when chips are stacked together. It can be seen that electromigration failure of micro-bump will become a severe issue. Investigation of electromigration reliability for fine pitch micro-bump is urgently needed. However, due to the extremely narrow gap between micro-bumps, reliability study through experimental methods is usually resource-consuming. Therefore, numerical simulation method is particularly important to study electromigration reliability. In this paper, a 3D stacked test vehicle model with Cu-Sn micro-bump as interlayer connection is established. Atomic Flux Divergence (AFD) method is used to investigate the dominate migration principle in Cu-Sn micronstructure under different working conditions. Results reveal the behavior of electronic migration, thermal migration, and stress migration under different electromigration test conditions. Stress migration is observed larger than electronic migration and thermal migration when current density=1x10(9)A/m(2), temperature=150 degrees C, which is in accordance with the experiment under the same condition. Besides, stress migration is observed always having great influence on electromigration process with different current density when test temperature is high (150 degrees C). Low test temperature is suggested if the effect of electronic migration needs to be manifested in final experiment result.
引用
收藏
页数:5
相关论文
共 26 条
  • [21] Three-dimensional Simulation of the Thermo-Mechanical Interaction between the Micro-bump Joints and Cu Protrusion in Cu-filled TSVs of the High Bandwidth Memory (HBM) Structure
    Zhou, Jie-Ying
    Liang, Shui-Bao
    Wei, Cheng
    Le, Wen-Kai
    Ke, Chang-Bo
    Zhou, Min-Bo
    Ma, Xiao
    Zhang, Xin-Ping
    2019 IEEE 69TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2019, : 410 - 416
  • [22] The Effect of the SnAg Solder Joint Morphology on the Thermal Cycle Reliability of 40 μm Fine-pitch Cu-pillar/SnAg Micro Bump Interconnection
    Lee, SeYong
    Lee, HanMin
    Park, JongHo
    Shin, SangMyung
    Kim, WooJeong
    Choi, TaeJin
    Paik, Kyung-Wook
    2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 649 - 654
  • [23] Effect of Material Properties of Double-Layer Non Conductive Films (D-NCFs) On the Reflow Reliability of Ultra Fine-pitch Cu-pillar/Sn-Ag Micro Bump Interconnection
    Lee, SeYong
    Shin, JiWon
    Kim, Woojeong
    Choi, Taejin
    Paik, Kyung-Wook
    2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, : 2110 - 2115
  • [24] Effect of the Curing properties and Viscosities of Non-Conductive Films (NCFs) On Ultra-Fine Pitch Cu-pillar/Sn-Ag Bump Joint Morphology and Reliability
    Lee, HanMin
    Choi, TaeJin
    Park, SooIn
    Paik, Kyung-Wook
    2019 IEEE 21ST ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2019, : 586 - 590
  • [25] Reliability study of 3D IC structure under thermal power consumption load by Finite Element Simulation
    Yuan, Hang
    Ma, Haoran
    Guo, Tianhao
    Xing, Jing
    Guo, Ying
    Ma, Haitao
    2022 23RD INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT, 2022,
  • [26] 3D Finite Element Simulation Study of Chip Stacking Structure Considering Different Numbers of Stacked Dies and the Effects of Underfill and Intermetallic Compound Layer of Micro joints
    Yang, Bing-Xian
    Fei, Jiu-Bin
    Liang, Shui-Bao
    Zhou, Min-Bo
    Hu, Wei-Lin
    Huang, Hai-Jun
    Zhang, Xin-Ping
    IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021), 2021, : 1405 - 1411