TENG: A General-Purpose and Efficient Processor Architecture for Accelerating DNN

Deep learning has been widely deployed in the fields such as computer vision and speech, etc. However, with the development of deep learning algorithms, neural networks have gradually become more complex, the subsequent computing requirements for huge amounts of data have posed greater challenges to hardware updates and improvements. In this work, a general-purpose and efficient deep neural network (DNN) accelerator is proposed, named TENG. In TENG, we proposed a unified architecture with general and dedicated coexistence to support various network operators, and the memory access engine in TENG optimizes off-chip data transmission to achieve better bandwidth utilization. The correctness of TENG is verified on FPGA and implemented in 7-nm FinFET technology. It achieves 4TOPS peak throughput@INT16 and has an energy efficiency of 5.15TOPS/W using VGG-16 at 1GHz clock frequency.